s in tel M2732A 32K (4K x 8) UV ERASABLE PROM Military m 250 ns (M2732A-25) Maximum Access a Industry Standard Pinout ... JEDEC Time ... HMOS* -E Technology Approved w Compatible to High Speed 5 MHz w Two Line Control MiAPX 86/10 MPU ... Zero Wait State w Low Standby Current... 35 mA Max. w Military Temperature Range: 55C to + 125C (Tc) The Intel M2732A is a 5V only, 32,768 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The standard M2732As access time is 450 ns with speed selection (M2732A-25) available at 250 ns. The access time is compatible to high performance microprocessors, such as the 5 MHz MiAPX 86/10. In these systems, the M2732A allows the microprocessor to operate without the addition of WAIT states. An important M2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (GE). The OE control eliminates bus contention in multipte bus microprocessor systems. Intel's Application Note AP-72 describes the microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP-72 is available from Inte!s Literature Department. The M2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum active current is 115 mA, while the maximum standby current is only 35 mA, a 66% saving. The standby mode is achieved by applying a TTL-high signal to the CE input. The M2732A ig fabricated with HMOS-E technology, Intels high speed N-channel MOS Silicon Gate Technol- ogy. *HMOS is a patented process of Inte! Corporation. DATA OUTPUTS M2732A vcc O 99-07 GND O Ta A Vpp O- 71 Voc a as(j2 Aa OE = - _OE AND as] 3 Ag cE OUTPUT BUFFERS CE Locic mace Ans = DECoDER 2 Y-GATING aC 5 OE/Vpp a sate A10 Ag-Ant : at? cE INPUTS = x : 32.769-BIT Aot]s o7 u Decopen | CELL MATRIX : oof] 06 of Os 271007-1 02 O4 Figure 1. Block Diagram GND 03 Mode Selection 271007-2 Figure 2. Configuration Pins | cE | OE/Vpp | Vcc| Outputs 8 - - P mes Mode (18) (20) (24) | (9-11, 13-17) r in . Read ViL Vit +5 Dout Chi coe Standby Vin, | Dont Care | +5 High Z OE 0 ~P ~ 7 t Program Vit Vpp +5 Din On0 a nae - tout: Program Verify | Vit | Vit +5 Dout oN? ufputs Program Inhibit | Vin Vpp +5 High Z October 1986 7-8 Order Number: 27 1007-001intel M2732A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias 55C to + 136C Storage Temperature .......... 65C to + 150C All Input or Output Voltages with Respect to Ground.............. +6V to 0.3V Vpp Supply Voltage with Respect to Ground During Programming ....+22V to 0.3V NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. * WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. AND A.C. OPERATING CONDITIONS DURING READ M2732A-25 M2732A-45 Operating Temperature Range (Tc) 55C to + 125C 55C to + 125C Voc Power Supply 5V 410% 5V +10% READ OPERATION D.C. CHARACTERISTICS Symbol Parameter Limits Unit Test Conditions Min Typ() Max he Input Load Current 10 pA Vin = 5.5V Ito Output Leakage Current 10 pA Vout = 5.5V Ioc1 Voc Current (Standby) 35 mA | CE = Vin. OE = ViL Ioce Voc Current (Active) 115 mA | OE =CE=ViL ViL Input Low Voltage 0.1 0.8 v Vin Input High Voltage 2.0 Voc + 1 Vv VoL Output Low Voitage 0.45 v lo. = 2.1 mA Vou Output High Voltage 2.4 v lon +400 pA NOTE: 1. Typical values are for Tc = 25C and nominal supply voltages. A.C. CHARACTERISTICS Symbol Parameter M2732A-25 M2732A~45 Unit Cc Test Min | Typ(t) | Max | Min | Typ(*) | Max onditions tacc Address to Output Delay 250 450 | ns | CE = OE = ViL tce CE to Output Delay 250 450 | ns | OF = ViL toe Output Enabie to Output 10 100; 10 150 | ns | CE = Vi_ Delay tpr(2) | Output Enable High to Output | 0 90 | 0 130 | ns | CE = Vit Float ton) | Output Hold from Addresses, | 0 0 ns | CE = OF = Vi CE or OE Whichever Occurred First 7-9intel M2732A CAPACITANCE (1), (2) Tc(S) = 25C, f = 1 MHz Symbol Parameter Typ} Max /| Unit! Conditions Cin Input Capacitance 4] 6 | pF iVin = OV Except OE/Vpp CIN OE/Vpp Input 20 | pF Vin = OV Capacitance Cout | Output Capacitance 12 | pF |Vour = OV A.C. TESTING, OUTPUT WAVEFORM A.C. TEST CONDITIONS a 2.0 20 > TEST POINTS < os a8 0.45 271007-5 A.C. Testing: inputs are driven at 2.4V for a Logic 1 and 0.45V for a Logic 0. Timing Measurements are made at 2.0V for a Logic 1 and 0.8V for a Logic 0. Output Load ...............006, 1 TTL gate, 1000 Resistor and C_ = 100 pF Input Rise and Falt Times ..........-..-..- <20 ns Input Pulse Levels .............-.66- 0.45V to 2.4V Timing Measurement Reference Level TC 1 | 0.8V and 2V Outputs ..... 02. cee eee eee 0.8V and 2V A.C. TESTING LOAD CIRCUIT 1.3 1NOI4 33K0 DEVICE. UNDER our TEST T = 100 pF C_ = 100 pF " 271007-6 C, includes Jig Capacitance A.C. WAVEFORMS ADDRESSES ADDRESSES VALID K K sees _7 cE lf ce OE f L isesssseeessssnees od tpgl4l toel3] - taccl3], _} on > . HIGH Z TI 777) HIGH Z ouTPUT < VALID OUTPUT 271007-3 NOTES: 1. Typical values are for To = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tacc-tog after the falling edge of CE without impact on tacc. 4. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven. 5. Case temperatures are instant on.intel M2732A DEVICE OPERATION The five modes of operation of the M2732A are list- ed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for OE/Vpp during programming. In the program mode the OE/Vpp input is pulsed from a TTL level to 21V. Table 1. Mode Selection PINS | CE | OE/Vpp |Vcc| Outputs Mode (18) (20) (24) | (9-11, 13-17) Read Vit Vit +5 Dout Standby Vin | Dont Care | +5 High Z Program VIL Vpp +5 Din Program Verify | Vi. ViL +5 Dout Program Inhibit | Vig] Vep | +5 High Z Read Mode The M2732A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equa! to the delay from CE to output (tce). Data is available at the outputs after the falling edge of OE, assuming that CE has been jow and addresses have been sta- ble for at least tacctoe. Standby Mode The M2732A has a standby mode which reduces the active power current by 66%, from 115 mA to 35 mA. The M2732A is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high imped- ance state, independent of the OE input. Output OR-Tieing Because EPROMs are usually used in larger memo- ry arrays, Intel has provided a 2 line control function that accommodates this use of multiple memory connection. The two line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the outputs pins are only active when data is desired from a particular memo- ry device. Programming Programming is the same as Intel's M2732 except for the programming voltage. In the program mode the M2732A OE/Vpp input is pulsed from a TTL low level to 21V (25V for the M2732). Exceeding 21.5V will damage the M2732A. Initially, and after each erasure, all bits of the M2732A are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Although only 0s will be programmed, both 1's and 0s can be present in the data word. The only way to change a 0 to a 1 is by ultraviolet light erasure. The M2792A is in the programming mode when the OE/Vpp input is at 21V. It is required that a 0.1 pF capacitor be placed across OE/Vpp and ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, a 50 ms, active low, TTL program pulse is applied to the CE input. A program pulse must be applied at each ad- dress location to be programmed. You can program any location at any timeeither individually, sequen- tially, or at random. The program pulse has a maxi- mum width of 55 ms. The M2732A must not be pro- grammed with a DC signa! applied to the CE input. Programming of the multiple M2732As in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled M2732As may be con- nected together when they are programmed with the same data. A low level TTL pulse applied to the CE input programs the paralleled M2732As.intel M2732A Program Inhibit Programming of multiple M2732As in parallel with different data is also easily accom lished. Except for CE, all like inputs (including OE) of the parallel M2732As may be common. A TTL level progam pulse applied to a M2732A's CE input with OE/V at 21V will program that M2732A. A high level te input inhibits the other M2732As from being pro- grammed. Program Verify A verify should be performed on the programmed bits to determine that they were correc pro- grammed. The verify is accomplished with OE/Vpp and GE at Vi_. Data should be verified tpy after the falling edge of CE. ERASURE CHARACTERISTICS The erasure characteristics of the M2732A are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 PROGRAMMING Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase the typical M2732A in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M2732A is to be exposed to these types of lighting conditions for extended periods of time, opaque la- bels should be placed over the M2732A window to prevent unintentional erasure. The recommended erasure procedure for the M2732A is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/em2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M2732A should be placed within 1 inch of the lamp tubes during era- sure. Some lamps have a filter on their tubes which should be removed before erasure. D.c. PROGRAMMING CHARACTERISTICS(1) To = 25C +5C; Voc = 5V 5%; Vpp = 21V +0.5V Symbol Parameter Limits Test Conditions Min | Typ| Max | Unit te Input Current (Ail inputs) 10 pA | Vin = Vic Or Vin Vor Output Low Voltage During Verify 0.45 V |iop = 2.1mA Vou Output High Voltage During Verify 2.4 V | low = 400 pA loc Voc Supply Current 85 125 mA ViL (Input Low Level (All Inputs) 0.1 0.8 Vv Vin Input High Level (All Inputs Except OE/Vpp) | 2.0 Veo +1} V Ipp Vpp Supply Current 35 mA | CE = Vi, OE = Vpp NOTE: 1. When programming the M2732A, a 0.1 F capacitor is required across OE/Vpp and ground to suppress spurious voltage transients which may damage the device. 7-12intel M2732A A.C. PROGRAMMING CHARACTERISTICS To = 25C +5C; Voc = 5V +5%: Vpp = 21V +0.5V Symbol Parameter Limits Test Conditions* Min Typ Max Unit tas Address Setup Time 2 ws toes OE Setup Time 2 ps tos Data Setup Time 2 BS tay Address Hold Time 0 BS toEH OE Hold Time 2 ps tbH Data Hold Time 2 us tor Chip Enable to Output Float Delay 0 130 ns tov Data Valid from CE 1 ws CE = Vi. OE = Vit tpw CE Pulse Width During Programming 45 50 55 ms tprt OE Pulse Rise Time During Programming 50 ns tva Vpp Recovery Time 2 ps *A.C. TEST CONDITIONS input Rise and Fall Times (10% to. 90%)...... 20 ns Input Pulse Levels .................. 0.45V to 2.4V Input Timing Reference Level! ....... 1.0V and 2.0V Output Timing Reference Level...... 0.8V and 2.0V PROGRAMMING WAVEFORMS PROGRAM ean ADDRESSES ADORESSN tas ta DATAIN STABLE Hid DATA QUT VALID 7 oA ADD N a00 N os fon, oF Legere te On e} ov e pam 10 13) lai 2. 1 Max an Qh: (ahem) {oat 10 05! _/ 271007-4 ______, NOTES: 1. All times shown in () are minimum and in ys unless otherwise specified. 2. The input timing reference level is 1V for a Vi_ and 2V for a Vip. 7-13