SCOPE: CMOS, 12-BIT BUFFERED, MULTIPLYING D/A CONVERTER
Device Type Generic Number
01 MX7545S(x)/883B
02 MX7545T(x)/883B
03 MX7545U(x)/883B
04 MX7545GU(x)/883B
Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
Outline Letter Mil-Std-1835 Case Outline Package Code
MAXIM SMD
Q R GDIP1-T20 or CDIP2-T20 20 LEAD CERDIP J20
E 2 CQCC1-N20 20 LCC L20
A bsolut e Maximum Rat ing s:
VREF to GND ...............................................................................................……. -0.3V, + 17V
Digital Input to DGND ...............................................................................…..... -0.3V to VDD
VRFB to GND ...........................................................................................................……. ±25V
VREF to GND ...........................................................................................................……. ±25V
VOUT1 to AGND ..........................................................................................……. -0.3V to VDD
AGND to DGND ........................................................................................……. -0.3V to VDD
Lead Temperature (soldering, 10 seconds) ........................................................................ +300°C
Storage Temperature ........................................................................................... -65°C to +150°C
Continuous Power Dissipation ..........................................................................…….. TA=+70°C
20 pin CERDIP(derate 11.1mW/°C above +70°C) .................................................…….. 889mW
20 pin LCC(derate 9.1mW/°C above +70°C) ..........................................................……. 727mW
Junct ion Temperature TJ ....................................................................................…….... +150°C
Thermal Resista nce, J unction to Case, ΘJC
20 pin CERDIP................................................................................................…….... 40°C/W
20 pin LCC .....................................................................................................………. 20°C/W
Thermal Resistance, Junction to Ambient, ΘJA:
20 pin CERDIP................................................................................................…….... 90°C/W
20 pin LCC ...................................................................................................………. 110°C/W
Recommended Operating Co ndit ions
Ambient Operating Range (TA) .........................................................……….. -55°C to +125°C
Supply Voltage Range .............................................................................………... +5V to +15V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions be yond
those indicated in the operational section s of the sp ecifica tions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
---------------------------- Electrical Characteristics of MX7545/883B for 19-0277 Rev. C
SMD 5962-87702 Page 2 of 7
TABLE 1. ELECTRICAL TESTS:
TEST Symbol
CONDITIONS
-55 °C TA +125°C 1/
Unless otherwise specified Group A
Subgroup Device
type Limits
Min Limits
Max Units
Resolution NOTE 4 RES VDD=+5V and +15V All 12 Bits
Relative Accuracy RA VDD=+5V and +15V 1,2,3 01
02
03,04
±2.0
±1.0
±0.5
LSB
Differential Nonlinearity DNL
10-bit monotonic, VDD=+5V and
+15V
12-bit monotonic, VDD=+5V and
+15V
1,2,3
01
02,03,
04
±4.0
±1.0
LSB
Gain Error NOTE 3 AE
VDD=5V 1,2,3
1
2,3
1
2,3
01
02
03
04
±20
±10
±5.0
±6.0
±1.0
±2.0
LSB
Gain Error NOTE 3 AE
VDD=15V 1,2,3
1
2,3
01
02
03
04
±25
±15
±10
±6.0
±7.0
LSB
Gain Temperature
Coefficient NOTE 4 TCAE VDD=+5V
VDD=+15V All ±5
±10
ppm/°C
Power Supply Rejection PSRR VDD=±5%, VDD=5V
VDD=±5%, VDD=15V
1
2,3
1
2,3
All
±0.015
±0.03
±0.01
±0.02
%/%
Out1 Leakage Current IOUT1 VDD=+5V & +15V, ___ __
D0-D11=0V, WR=CS=0V 1
2,3 All ±10
±200 nA
Feedthrough Error
NOTE 4, NOTE 5 FTE VREF=±10V, 10kHz sine wave
VDD=5V
VREF=±10V, 10kHz sine wave
VDD=15V
4,5,6 All 10 mVp-p
Input Resistance RIN VDD=+5V and +15V 1,2,3 All 725
k
Digital Input High
Voltage VIH VDD=+5V
VDD=+15V 1,2,3 All 2.4
13.5
V
Digital Input Low
Voltage VIL VDD=+5V
VDD=+15V 1,2,3 All 0.8
1.5 V
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SMD 5962-87702 Page 3 of 7
TEST Symbol
CONDITIONS
-55 °C TA +125°C 1/
Unless otherwise specified Group A
Subgroup Device
type Limits
Min Limits
Max Units
Digital Input Leakage
Current IIN VIN=0V or VDD
VDD=+5V or +15V 1
2,3 All ±1.0
±10 µA
Digital Input Capacitance
NOTE 2, NOTE 6 CIN
D0-D11, VDD=5V
___ __
WR, CS, VDD=5V
D0-D11, VIN=0V, VDD=15V
___ __
WR, CS, VIN=0V, VDD=15V
4All
5
20
5
20
pF
Output Capacitance
NOTE 2, NOTE 6 COUT1
VDD=5V ___ __
D0-D11=0V, WR, CS=0V
VDD=5V ___ __
D0-D11=VDD, WR, CS=0V
VDD=15V ___ __
D0-D11=0V, WR, CS=0V
VDD=15V ___ __
D0-D11=VDD, WR, CS=0V
4All
70
200
70
200
pF
Chip Select to W rite-
Setup Time NOTE 7 tCS VDD=5V
VDD=15V 9,10,11 All 170
95 ns
Chip Select to W rite-Hold
Time NOTE 7 tCH VDD=+5V and +15V 9,10,11 All 0ns
Write Pulse Width NOTE
7tWR tCS±tWR, tCH±0, VDD=+5V
tCStWR, tCH0, VDD=15V
9,10,11 All 170
95 ns
Data-Setup Time
NOTE 7 tDS VDD=5V
VDD=15V
9,10,11 All 150
80 ns
Data-Hold Time NOTE 7 tDH VDD=+5V and +15V 9,10,11 All 5ns
Supply Current IDD
All digital inputs VIL or VIH
VDD=+5V and +15V
All digital inputs 0V or VDD
VDD=+5V and +15V
1,2,3
1
2,3
All
2.0
100
500
mA
µA
NOTE 1: VDD=+15V, VOUT1=0V; VREF=+10V, AGND=DGND, unless o therwise specified.
NOTE 2: These parameters may be guaranteed if not tested at 25°C to the limits specified in T a ble 1.
NOTE 3: Measured using internal feedback resistor and includes effect of 5ppm max gain TC.
NOTE 4: These parameters may be guaranteed if not tested over the full military temp range to the
limits specified in Table 1.
NOTE 5: Fee dthro ugh error can be reduced by connect ing the metal lid on the package to ground.
NOTE 6: Subgroup 4 (CIN measurement) shall be measured only for the initial test a nd after process
or design changes which may affect capacitance.
NOTE 7: Timing Diagram. See Commercial Datasheet.
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SMD 5962-87702 Page 4 of 7
ORDERING INFORMATION:
Package Pkg. Code MAXIM PART # SMD Number
01 20 pin CERDIP J20 MX7545SQ/883B 5962-8770201RA
01 20 pin LCC L20 MX7545SE/883B 5962-87702012C
02 20 pin CERDIP J20 MX7545TQ/883B 5962-8770202RA
02 20 pin LCC L20 MX7545TE/883B 5962-87702022C
03 20 pin CERDIP J20 MX7545UQ/883B 5962-8770203RA
03 20 pin LCC L20 MX7545UE/883B 5962-87702032C
04 20 pin CERDIP J20 MX7545GUQ/883B 5962-8770204RA
04 20 pin LCC L20 MX7545GUE/883B 5962-87702042C
TERMINAL CONNECTIONS:
J20 & L20
Pin
1 OUT1
2AGND
3 DGND
4 D11(MSB)
5D10
6D9
7D8
8D7
9D6
10 D5
11 D4
12 D3
13 D2
14 D1
15 D0(LSB)
16 __
CS
17 ___
WR
18 VDD
19 VREF
20 RFB
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SMD 5962-87702 Page 5 of 7
QUALITY ASSURAN CE
Sampling and inspection procedures shall be in accordance with MIL-Prf-38535, Appendix A as specified in Mil-
Std-883.
Screening shall be in accordance with Method 5004 of Mil-Std-883. Burn-in test Method 1015:
1. Test Condition, A, B, C, or D.
2. TA = +125°C minimum.
3. Interim and final electrical test requirements shall be specified in Table 2.
Quality conformance inspection shall be in accordance with Method 5005 of Mil-Std-883, including Groups A, B,
C, and D inspection.
Group A inspection:
1. Tests as specified in Table 2.
2. Selected subgroups in Table 1, Method 5005 of Mil-Std-883 shall be omitted.
Group C and D inspections:
a. End-point electrical parameters shall be specified in Table 1.
b. Steady-state life test, Method 1005 of Mil-Std-883:
1. Test condition A, B, C, D.
2. TA = +125°C, minimum.
3. Test duration, 1000 hours, except as permitted by Method 1005 of Mil-Std-883.
TABLE 2. ELECTRICAL TEST REQUIREM ENTS
Mil-Std-883 Test Requirements Subgroups
per Method 5005, Table 1
Interim Electric Parameters
Method 5004 1
Final Electrical Parameters
Method 5005 1*, 2, 3
Group A Test Requirements
Method 5005 1, 2, 3, 4**, 5, 6, 9, 10***, 11***
Group C and D End-Point Electrical Parameters
Method 5005 1
* PDA applies to Subgroup 1 only.
** Subgroup 4 shall be tested at initial qualification and upon redesign. Sample size will
be 116 units.
*** Subgroups 10 and 11, if not test ed shall be guaranteed to the specifi ed limi t s of Table 1.
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