REV. 0
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otherwise under any patent or patent rights of Analog Devices.
a
ADM691A/ADM693A/ADM800L/M
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
Microprocessor
Supervisory Circuits
FUNCTIONAL BLOCK DIAGRAM
CHIP ENABLE
OUTPUT
CONTROL
VBATT
VCC
CEIN
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
ADM691A/ADM693A
ADM800L/ADM800M
1.25V
WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE
RESET &
GENERATOR
4.65V1
BATT ON
LOW LINE
VOUT
CEOUT
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
WATCHDOG
TRANSITION DETECTOR
FEATURES
Low Power Consumption:
Precision Voltage Monitor
62% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 mA Standby Current
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring
GENERAL DESCRIPTION
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include µP reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
V
CC
as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than +5 V.
VBATT
VCC
CMOS
RAM
CEIN
OSC IN
OSC SEL
BAT
ON
LOW LINE
VOUT
CEOUT
RESET RESET
PFO
WDI
VCC
WDO
I/O LINE
NMI
A0–A15 µP
POWER
µP
ADDRESS
DECODE
ADM691A
ADM693A
ADM800L
ADM800M
GND
PFI
BATTERY
0.1µF
+5V
NC
R2
R1
INPUT
POWER
7805
SYSTEM
STATUS
INDICATORS
Figure 1. Typical Application
ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS
–2– REV. 0
(VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted)
Parameter Min Typ Max Unit Test Conditions/Comments
BATTERY BACKUP SWITCHING
V
CC
, V
BATT
Operating Voltage Range 0 5.5 V
V
OUT
Output Voltage V
CC
– 0.05 V
CC
– 0.02 V I
OUT
= 25 mA
V
CC
– 0.3 V
CC
– 0.2 V I
OUT
= 250 mA
V
CC
to V
OUT
Output Resistance 0.8 1.2 ΩV
CC
= 4.5 V
V
OUT
in Battery Backup Mode V
BATT
– 0.3 V V
BATT
= 4.5 V, I
OUT
= 20 mA
V
BATT
– 0.25 V V
BATT
= 2.8 V, I
OUT
= 10 mA
V
BATT
– 0.15 V V
BATT
= 2.0 V, I
OUT
= 5 mA
V
BATT
to V
OUT
Output Resistance 12 ΩV
BATT
= 4.5 V
20 ΩV
BATT
= 2.8 V
25 ΩV
BATT
= 2.0 V
Supply Current (Excludes I
OUT
) 70 100 µAV
CC
> (V
BATT
– 1 V)
Supply Current in B. Backup (Excludes I
OUT
) 0.04 1 µAV
CC
< (V
BATT
– 1.2 V), V
BATT
= 2.8 V
Battery Standby Current 5.5 V > V
CC
> V
BATT
+ 0.2 V
(+ = Discharge, – = Charge) –0.1 +0.02 µA(V
BATT
+0.2 V) < V
CC
, T
A
= +25°C
–1.0 +0.02 µA(V
BATT
+0.2 V) < V
CC
Battery Switchover Threshold V
BATT
+ 0.03 V Power Up
V
CC
–V
BATT
V
BATT
– 0.03 V Power Down
Battery Switchover Hysteresis 60 mV
BATT ON Output Voltage Low 0.1 0.4 V I
SINK
= 3.2 mA
0.7 1.5 V I
SINK
= 25 mA
BATT ON Output Short Circuit Current 60 mA Sink Current
1 15 100 µA Source Current
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM691A, ADM800L 4.5 4.65 4.75 V
ADM693A, ADM800M 4.25 4.40 4.50 V
ADM800L, V
CC
Falling 4.55 4.70 V T
A
= +25°C
ADM800M, V
CC
Falling 4.3 4.45 V T
A
= +25°C
Reset Threshold Hysteresis 15 mV
V
CC
to RESET Delay 80 µs Power Down
LOW LINE to RESET Delay 800 ns
Reset Timeout Period Internal Oscillator 140 200 280 ms Power Up
Reset Timeout Period External Clock 2048 Cycles Power Up
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period
70 100 140 ms Short Period
Watchdog Timeout Period, External Clock 4096 Cycles Long Period
1024 Cycles Short Period
Minimum WDI Input Pulse Width 100 ns V
IL
= 0.4, V
IH
= 0.75 × V
CC
RESET Output Voltage 0.004 0.3 V I
SINK
= 50 µA, V
CC
= 1 V, V
BATT
= 0 V
0.1 0.4 V I
SINK
= 3.2 mA, V
CC
= 4.25 V
3.5 V I
SOURCE
= 1.6 mA, V
CC
= 5 V
RESET Output Short Circuit Current 7 20 mA
RESET Output Voltage Low 0.1 0.4 V I
SINK
= 3.2 mA
LOW LINE Output Voltage 0.4 V I
SINK
= 3.2 mA, V
CC
= 4.25 V
3.5 V I
SOURCE
= 1 µA, V
CC
= 5 V
LOW LINE Short Circuit Source Current 1 15 100 µA
WDO Output Voltage 0.4 V I
SINK
= 3.2 mA, V
CC
= 4.25 V
3.5 V I
SOURCE
= 500 µA, V
CC
= 5 V
WDO Short Circuit Source Current 3 10 mA
WDI Input Threshold
Logic Low 0.8 V
Logic High 0.75 × V
CC
V
WDI Input Current –50 –10 µA WDI = 0 V
20 50 µA WDI = V
OUT
POWER FAIL DETECTOR
PFI Input Threshold ADM69xA 1.2 1.25 1.3 V V
CC
= 5 V
PFI Input Threshold ADM800L/M 1.225 1.25 1.275 V V
CC
= 5 V
PFI Input Current ±0.01 ±25 nA
PFO Output Voltage 0.4 V I
SINK
= 3.2 mA
3.5 I
SOURCE
= 1 µA
PFO Short Circuit Source Current 1 15 100 µA
PFI to PFO Delay 25 µsV
IN
= –20 mV
60 µsV
IN
= 20 mV
–3–
REV. 0
ADM691A/ADM693A/ADM800L/M
Parameter Min Typ Max Units Test Conditions/Comments
CHIP ENABLE GATING
CE
IN
Leakage Current ±0.005 ±1µA Disable Mode
CE
IN
to CE
OUT
Resistance 40 150 ΩEnable Mode
CE
IN
to CE
OUT
Propagation Delay 6 10 ns R
IN
= 50 Ω, C
LOAD
= 50 pF
CE
OUT
Short-Circuit Current 0.1 0.75 2.0 mA Disable Mode, CE
OUT
= 0 V
CE
OUT
Output Voltage 3.5 V V
CC
= 5 V, I
OUT
= –100 µA
2.7 V V
CC
= 0 V, V
BATT
= 2.8 V, I
OUT
= 1 µA
RESET to CE
OUT
Propagation Delay 12 µs Power Down
OSCILLATOR
OSC IN Input Current 0.1 ±5µA OSC SEL = 0 V
OSC In Input Pullup Current 10 100 µA OSC SEL = V
OUT
or Floating
OSC SEL Input Pullup Current 10 100 µA OSC SEL = 0 V
OSC IN Frequency Range 500 kHz OSC SEL = 0 V
OSC IN Threshold Voltage V
OUT
– 0.4 V
OUT
– 0.6 V V
IH
3.65 2.00 V V
IL
OSC IN Frequency with Ext Capacitor 100 kHz OSC SEL = 0 V, C
OSC
= 47 pF
NOTES
1
Either V
CC
or V
BATT
can be 0 V if the other > +2.0 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V
OUT
+ 0.5 V
Input Current
V
CC
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA
V
CC
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
V
BATT
(Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
V
BATT
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW
θ
ϑA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .110°W
Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
Table I. Product Selection Table
Power On Low V
CC
Watchdog Battery Backup Base Drive Chip Enable
Part No. Reset Time Threshold Timeout Switching Ext PNP Signals
ADM691A 200 ms or Adj. 4.65 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM693A 200 ms or Adj. 4.4 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM800M 200 ms or Adj. 4.4 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes
ADM800L 200 ms or Adj. 4.65 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes
ORDERING GUIDE
Temperature Package
Model Range Option
ADM691AAN –40°C to +85°C N-16
ADM691AARN –40°C to +85°C R-16N
ADM691AARW –40°C to +85°C R-16W
ADM691AARU –40°C to +85°C RU-16
ADM693AAN –40°C to +85°C N-16
ADM693AARN –40°C to +85°C R-16N
ADM693AARW –40°C to +85°C R-16W
ADM800LAN –40°C to +85°C N-16
ADM800LARN –40°C to +85°C R-16N
ADM800LARW –40°C to +85°C R-16W
ADM800MAN –40°C to +85°C N-16
ADM800MARN –40°C to +85°C R-16N
ADM800MARW –40°C to +85°C R-16W
ADM691A/ADM693A/ADM800L/M
–4– REV. 0
PIN DESCRIPTIONS
Pin Mnemonic Function
1V
BATT
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
2V
OUT
Output Voltage, V
CC
or V
BATT
is internally switched to V
OUT
depending on which is at the highest poten-
tial. When V
CC
is higher than V
BATT
and is also higher than the reset threshold, V
CC
is switched to V
OUT
.
When V
CC
is lower than V
BATT
and below the reset threshold, V
BATT
is switched to V
OUT
. Connect V
OUT
to
V
CC
if a backup battery is not being used.
3V
CC
Power Supply Input; +5 V.
4 GND 0 V. Ground reference for all signals.
5 BATT ON Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input. It goes low when
V
OUT
is internally switched to V
CC
. The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of V
OUT
.
6LOW LINE Logic Output. LOW LINE goes low when V
CC
falls below the reset threshold. It returns high as soon as
V
CC
rises above the reset threshold.
7 OSC
IN Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC
IN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
8 OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC
IN, is enabled. OSC SEL has a 10 µA internal pullup.
9 PFI Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V, PFO goes low. Connect PFI to GND or V
OUT
when not used.
10 PFO Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
11 WDI Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
12 CE
OUT
Output. CE
OUT
goes low only when CE
IN
is low and V
CC
is above the reset threshold. If CE
IN
is low when
reset is asserted, CE
OUT
will remain low for 15 µs or until CE
IN
goes high, whichever occurs first.
13 CE
IN
Chip Enable Input. The input to the CE gating circuit. Connect to GND or V
OUT
if not used.
14 WDO Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than
the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
15 RESET Logic Output. RESET goes low if V
CC
falls below the Reset Threshold. It remains low for 200 ms typ after
V
CC
goes above the reset threshold.
16 RESET Logic Output. RESET is an open-drain output. It is the inverse of RESET.
PIN CONFIGURATIONS
VBATT
CEIN
OSC IN
OSC SEL
BATT ON
LOW LINE
VOUT
CEOUT
RESET
RESET
PFO
WDI
VCC WDO
GND
PFI
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADM691A
ADM693A
ADM800L
ADM800M
ADM691A/ADM693A/ADM800L/M
–5–
REV. 0
Typical Performance Curves–
TEMPERATURE – °C
–50 125–25 0 25 50 75 100
100
20
V
CC
SUPPLY CURRENT – µA
70
40
30
90
80
60
50
Figure 2. I
CC
vs. Temperature: Normal Operation
TEMPERATURE – °C
–50 90–30 –10 10 30 50 70
60
30
BATTERY SUPPLY CURRENT – nA
45
40
35
55
50
Figure 3. I
BATT
vs. Temperature: Battery Backup Mode
TEMPERATURE – °C
–50 125–25 0 25 50 75 100
80
20
CE
ON
RESISTANCE – Ω
50
40
30
70
60
Figure 4. Chip Enable ON-Resistance vs. Temperature
TEMPERATURE – °C
–50 90–30 –10 10 30 50 70
1.2
0.6
V
CC
TO V
OUT
ON RESISTANCE – R
0.9
0.8
0.7
1.1
1.0
Figure 5. V
CC
to V
OUT
ON-Resistance vs. Temperature
I
OUT
– mA
80
040 120
V
CC
TO V
OUT
– mV
60 80 100
70
40
30
20
10
60
50
R
OUT
= 0.67Ω
Figure 6. V
CC
to V
OUT
Voltage Drop vs. Current
I
OUT
– mA
70
0410
V
BATT
TO V
OUT
– mV
68
60
50
40
20
10
30
R
OUT
= 7Ω
Figure 7. V
BATT
to V
OUT
Voltage Drop vs. Current
ADM691A/ADM693A/ADM800L/M
–6– REV. 0
V
CC
– V
0 5.00.5 1.0 1.5 2.0 2.5 3.0
10
0
I
BATT
– µA
7
2
1
9
8
6
5
4
3
3.5 4.0 4.5
V
BATT
= 2.8V
Figure 8. Battery Current vs. Input Supply Voltage
C
OSC
– pF
100
10
0.110 1k100
WATCHDOG AND RESET TIMEOUT PERIOD – s
1
LONG WATCHDOG TIMEOUT PERIOD
SHORT WATCHDOG
TIMEOUT PERIOD
RESET ACTIVE
TIMEOUT PERIOD = >
Figure 9. Watchdog and Reset Timeout Period vs.
OSC IN Capacitor
TEMPERATURE – °C
–50 125–25 0 25 50 75 100
7.0
4.0
PROPAGATION DELAY – ns
5.5
5.0
4.5
6.5
6.0
Figure 10. Chip Enable Propagation Delay vs.
Temperature
LOAD CAPACITANCE – pF
0 30050 100 150 200 250
16
0
10
4
2
14
12
8
6
PROPAGATION DELAY – ns
Figure 11. Chip Enable Propagation Delay vs.
Load Capacitance
TEMPERATURE – °C
–50 90–30 –10 10 30 50 70
230
170
RESET DELAY – ms
200
220
210
190
180
Figure 12. Reset Timeout Relay vs. Temperature
TEMPERATURE – °C
–50 130–20 10 40 70 100
1200
0
RESET OUTPUT RESISTANCE – Ω
600
1000
800
400
200
VCC = 5V, VBATT = 2.8V
SOURCING CURRENT
VCC = 0V, VBATT = 2.8V
SINKING CURRENT
Figure 13.
RESET
Output Resistance vs. Temperature
ADM691A/ADM693A/ADM800L/M
–7–
REV. 0
10
0%
100
90
400ms1V
Figure 14.
RESET
Output Voltage vs. Supply
10
0%
100
90
10µs
1V
Figure 15.
RESET
Response Time
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to the
Microprocessor whenever V
CC
is at an invalid level. When V
CC
falls below the reset threshold, the RESET output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up RESET will remain low for 200 milliseconds after
V
CC
rises above the appropriate reset threshold. This allows time
for the power supply and microprocessor to stabilize. On power-
down, the RESET output remains low with V
CC
as low as 1 V.
This ensures that the microprocessor is held in a stable shut-
down condition. If RESET is required to be low for voltages be-
low 1 V, this may be achieved by connecting a pull-down resistor
on the RESET line. The resistor will help maintain RESET low
down to V
CC
= 0 V. Note that this is only necessary if V
BATT
is
below 2 V. With battery voltages ≥2 V RESET will function cor-
rectly with V
CC
from 0 V to +5.5 V.
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran-
teed thresholds of the ADM693A/ADM800M are 4.25 V and
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V ± 10% supplies.
In addition to RESET an active high RESET output is provided.
This is the complement of RESET and is useful for processors
requiring an active high RESET signal.
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watch-
dog timeout period may be configured for either a fixed “short”
100 ms or a “long” 1.6 second timeout period or for an adjust-
able timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V
CC
falling be-
low the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
CHIP ENABLE
OUTPUT
CONTROL
V
BATT
V
CC
CE
IN
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
ADM691A/ADM693A
ADM800L/ADM800M
1.25V
WATCHDOG
TRANSITION DETECTOR WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE RESET &
GENERATOR
4.65V
1
BATT ON
LOW LINE
V
OUT
CE
OUT
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
Figure 16. Functional Block Diagram
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when V
CC
goes below the reset threshold. If WDI re-
mains high or low indefinitely, RESET and RESET will gener-
ate 200 ms pulses every 1.6 sec.
ADM691A/ADM693A/ADM800L/M
–8– REV. 0
Changing the Watchdog and Reset Timeout
The watchdog and reset timeout periods may be controlled us-
ing OSC SEL and OSC IN. Please refer to Table II. With both
these inputs floating (or connected to V
OUT
) as in Figure 16, the
reset timeout is fixed at 200 ms and the watchdog timeout is
fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure
16, the reset timeout period remains at 200 ms but a short
(100 ms) watchdog timeout period is selected (except immedi-
ately following a reset where it reverts to 1.6 sec). By connecting
OSC SEL to GND it is possible to select alternative timeout pe-
riods by either connecting a capacitor from OSC IN to GND or
by overdriving OSC IN with an external clock. With an external
capacitor, the watchdog timeout period is
Twd (ms) = 600 (C/47 pF)
and the reset active period is
Treset (ms) = 1200 (C/47 pF)
With an external clock connected to OSC IN, the timeout
periods become
Twd = 1024 (1/f
CLK
)
Treset = 2048 (1/f
CLK
)
Battery-Switchover Section
During normal operation with V
CC
higher than the reset thresh-
old and higher than V
BATT
, V
CC
is internally switched to V
OUT
via an internal PMOS transistor switch. This switch has a typi-
cal on-resistance of 0.75 Ω and can supply up to 250 mA at the
V
OUT
terminal. V
OUT
is normally used to drive a RAM memory
bank which may require instantaneous currents of greater than
250 mA. If this is the case then a bypass capacitor should be
connected to V
OUT
. The capacitor will provide the peak current
transients to the RAM. A capacitance value of 0.1 µF or greater
may be used.
If the continuous output current requirement at V
OUT
exceeds
250 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can drive
the base of the external transistor.
If V
CC
drops below V
BATT
and below the reset threshold, battery
backup is selected. A 7 Ω MOSFET switch connects the V
BATT
input to V
OUT
. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required for
battery backup of CMOS RAM or other low power CMOS cir-
cuitry. The supply current in battery backup is typically 0.04 µA.
High value capacitors, either standard electrolytic or the farad-
size double layer capacitors, can also be used for short-term
memory backup.
If the battery-switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
When V
CC
is below the reset threshold, the watchdog function is
disabled and WDI goes high impedance as it is disconnected
from its internal resistor network.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods.
CE
IN
RESET
RESET
V
CC
CE
OUT
OSC SEL
RESET
THRESHOLD 80µs
t
RS
12µs
t
RS
80µs
Figure 17. RESET and Chip Enable Timing
OSC SEL
OSC IN
7
8
ADM69_A
ADM800_
CLOCK
0 TO 250kHz
Figure 18a. External Clock Source
OSC SEL
OSC IN
7
8
ADM69_A
ADM800_
NC
NC
Figure 18b. Internal Oscillator (1.6 s Watchdog)
7
OSC SEL
OSC IN
8
ADM69_A
ADM800_
C
OSC
Figure 18c. External Capacitor
Table II. Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
OSC SEL OSC IN Normal Immediately After Reset Reset Active Period
Low External Clock Input 1024 clks 4096 clks 2048 clks
Low External Capacitor 600 ms × C/47 pF 2.4 s × C/47 pF 1200 ms × C/47 pF
Floating Low 100 ms 1.6 s 200 ms
Floating Floating or V
OUT
1.6 s 1.6 s 200 ms
ADM691A/ADM693A/ADM800L/M
–9–
REV. 0
7
OSC SEL
OSC IN
8
ADM69_A
ADM800_
C
OSC
Figure 18d. Internal Oscillator (100 ms Watchdog)
WDI
WDO
t
1
RESET
t
1
= RESET TIME.
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
t
1
t
1
t
2
t
3
Figure 19. Watchdog Timing
CE Gating and RAM Write Protection
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when V
CC
is at an invalid level. There are two additional pins,
CE
IN
and CE
OUT
, that control the Chip Enable or Write inputs
of CMOS RAM. When V
CC
is present, CE
OUT
is a buffered rep-
lica of CE
IN
, with a 5 ns propagation delay. When V
CC
falls be-
low the reset voltage threshold, an internal gate forces CE
OUT
high, independent of CE
IN
.
CE
OUT
typically drives the CE, CS, or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CE
OUT
to drive the Store or Write inputs of an
EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down proce-
dure executed before power is lost.
R2
PFO
1.25V
POWER
FAIL
INPUT POWER
FAIL
OUTPUT
R1
INPUT
POWER
Figure 20. Power Fail Comparator
Table III. Input and Output Status in Battery Backup Mode
Signal Status
V
BATT
Supply Current is <1 µA.
V
OUT
V
OUT
is connected to V
BATT
via an internal
PMOS switch.
V
CC
Switchover comparator monitors V
CC
for
active switchover.
GND 0 V.
BATT ON Logic High. The open circuit voltage is equal
to V
OUT
.
LOW LINE Logic Low.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
PFI The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥ V
BATT
–1.2 V. With V
CC
lower than this, PFO is
forced low.
PFO The Power Fail Comparator remains active in
the battery-backup mode for V
CC
≥ V
BATT
–1.2 V. With V
CC
lower than this, PFO is
forced low.
WDI WDI is ignored.
CE
OUT
Logic High. The open circuit voltage is equal
to V
OUT
.
CE
IN
High Impedance.
WDO Logic High. The open circuit voltage is equal
to V
OUT
.
RESET Logic Low.
RESET High Impedance.
ADM691A/ADM693A/ADM800L/M
–10– REV. 0
APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at V
OUT
exceeds
250 mA or if a lower V
CC
–V
OUT
voltage differential is desired, an
external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output can drive the
base of the external transistor via a current limiting transistor.
0.1µF
+5V
INPUT
POWER
VCC BATT
ON
VBATT
BATTERY
PNP
TRANSISTOR
VOUT
0.1µF
Figure 21. Increasing the Drive Current
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power
down if the resistor were connected to V
CC.
RECHARGEABLE
BATTERY
VOUT – VBATT
R
I =
R
ADM69_A
ADM800_
0.1µF
+5V
INPUT
POWER
VCC
VBATT
VOUT
0.1µF
Figure 22. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting,
hysteresis can be added simply by connecting a resistor between
the PFO output and the PFI input as shown in Figure 23. When
PFO is low, resistor R3 sinks current from the summing junction
at the PFI pin. When PFO is high, R3 sources current into the
PFI summing junction. This results in differing trip levels for the
comparator. Resistors R1 and R2 therefore set the trip point
while R3 adds hysteresis. R3 should be larger than 10 kΩ so that
it does not cause excessive loading on the PFO output. Addi-
tional noise rejection and filtering may be achieved by adding a
capacitor from PFI to GND.
1.25V (PFO)
INPUT
POWER
R1
R2
PFI
R3
TO
µP NMI
5V
PFO
0V 0V V
L
V
M
V
IN
V
H
=
1.25
1
+ R
1
R
2
+R
3
R
2
×
R
3
V
L
= 1
.25
+R
11.25
V
CC
–
1.25
R
2
R
3
V
MID
=
1.25
R
1
+R
2
R
2
Figure 23. Adding Hysteresis to the Power Fail Comparator
Typical Operating Circuit
A typical operating circuit is shown in Figure 24. The circuit
features power supply monitoring, battery backup switching
and watchdog timing.
CMOS RAM is powered from V
OUT
. When 5 V power is
present, this is routed to V
OUT
. If V
CC
fails, then V
BATT
is
routed to V
OUT
. V
OUT
can supply up to 250 mA from V
CC
, but
if more current is required, an external PNP transistor can be
added. When V
CC
is higher than V
BATT
and the reset threshold,
BATT ON goes low, providing base drive for the external tran-
sistor. When V
CC
is lower than V
BATT
and the reset threshold,
an internal 7 Ω. MOSFET connects the backup battery to
V
OUT
.
Reset Output
The internal voltage detector monitors V
CC
and generates a
RESET output to hold the microprocessor’s RESET line low
when V
CC
is below the reset threshold. An internal timer holds
RESET low for 200 ms after V
CC
rises above the threshold.
This prevents repeated toggling of RESET even if the 5 V
power drops out and recovers with each power line cycle.
Early Power Fail Detector
The input power line is monitored via a resistive potential di-
vider connected to the Power Fail Input (PFI). When the volt-
age at PFI falls below 1.25 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If a Power Fail threshold
of 7 V is set with resistors R1 and R2, the microprocessor will
have the time when V
CC
drops below 7 V to save data into
RAM. Power supply capacitance will extend the time available.
This will allow more time for microprocessor housekeeping
tasks to be completed before power is lost.
ADM691A/ADM693A/ADM800L/M
–11–
REV. 0
RAM Write Protection
The CE
OUT
line drives the Chip Select inputs of the CMOS
RAM. CE
OUT
follows CE
IN
as long as V
CC
is above the reset
threshold. If V
CC
falls below the reset threshold, CE
OUT
goes
high, independent of the logic level at CE
IN
. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The LOW LINE output goes low when V
CC
falls
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector RESET bus or directly drive a
CMOS gate without an external pullup resistor.
3V
BATTERY
0.1µF0.1µF
OSC IN
OSC SEL
GND
PFI
NC
0.1µF
RESET
WDO
LOW LINE
SYSTEM STATUS
INDICATORS
RESET
PFO
WDI
CE
IN
CE
OUT
V
BATT
R2
R1
CMOS
RAM
ADDRESS
DECODE
INPUT POWER
+5V
V
CC
BATT
ON V
OUT
A0–A15
I/O LINE
NMI
RESET
µ
P
ADM691A
ADM693A
ADM800L
ADM800M
Figure 24. Typical Application Circuit
ADM691A/ADM693A/ADM800L/M
–12– REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2198–12–10/96
PRINTED IN U.S.A.
16-Lead Plastic DIP
(N-16)
16
18
9
0.840 (21.33)
0.745 (18.93)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
16-Lead Wide SOIC
(R-16W)
16 9
81
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
16-Lead TSSOP
(RU-16)
16 9
8
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
16-Lead Narrow SOIC
(R-16N)
16 9
81
0.3937 (10.00)
0.3859 (9.80)
0.2550 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (5.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC 0.0099 (0.25)
0.0075 (0.19) 0.0500 (1.27)
0.0160 (0.41)
8°
0°
0.0196 (0.50)
0.0099 (0.25) x 45°
