Preliminary Information AMD Duron Processor essor Model 7 Data ta Sheet TM Publication # 24310 Rev: G Issue Date: January 2002 Preliminary Information (c) 2001, 2002 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, and 3DNow! are trademarks of Advanced Micro Devices, Inc. HyperTransport is a trademark of the HyperTransport Technology Consortium. MMX is a trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AMD DuronTM System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6 3 Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 4.2 4.3 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 13 Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 Table of Contents Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 26 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 27 VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 27 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VCC_CORE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 31 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 32 AMD Duron System Bus AC and DC Characteristics . . . . . . 34 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 36 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 41 iii Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 8 Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 43 8.1 8.2 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CPGA Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 10.2 10.3 iv Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Signal Sequence and Timing Description . . . . . . . . . . . . . 43 Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 46 Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 46 Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 9.2 9.3 10 24310G--January 2002 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 51 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 AMD Duron System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . 68 Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 68 CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 68 CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . 69 CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 69 FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . 71 Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . 72 Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . 73 Table of Contents Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Standard AMD Duron Processor Model 7 Products . . . . . . . . . . . . . 75 Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 77 Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table of Contents v Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 vi Table of Contents Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 List of Figures Figure 1. Typical AMD DuronTM Processor Model 7 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. AMD Duron Processor Model 7 Power Management States . . . 9 Figure 4. AMD Duron System Bus Disconnect Sequence in the Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 16 Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 32 Figure 10. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 11. General ATE Open Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 38 Figure 12. Signal Relationship Requirements During Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 13. AMD Duron Processor Model 7 CPGA Package . . . . . . . . . . . . 49 Figure 14. AMD Duron Processor Model 7 Pin Diagram-- Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 15. AMD Duron Processor Model 7 Pin Diagram-- Bottomside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 16. OPN Example for the AMD Duron Processor Model 7 . . . . . . . 75 List of Figures vii Preliminary Information AMD DuronTM Processor Model 7 Data Sheet viii 24310G--January 2002 List of Figures Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 List of Tables List of Tables Table 1. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 2. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . 28 Table 7. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 32 Table 10. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 33 Table 11. AMD DuronTM System Bus DC Characteristics . . . . . . . . . . . . . 34 Table 12. AMD Duron System Bus AC Characteristics . . . . . . . . . . . . . . . 35 Table 13. General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 36 Table 14. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 39 Table 15. Guidelines for Platform Thermal Protection of the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 16. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 41 Table 17. Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 18. Dimensions for the AMD Duron Processor Model 7 CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 19. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 20. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 21. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 70 Table 22. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 74 Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 24. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ix Preliminary Information AMD DuronTM Processor Model 7 Data Sheet x 24310G--January 2002 List of Tables Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Revision History Date Rev Description Changes for the AMD DuronTM Processor Model 7 Data Sheet since November 2001 include the following: January 2002 G In Chapter 6, revised Table 1, "Thermal Design Power," on page 23 In Chapter 7, revised Table 8, "VCC_CORE Voltage and Current," on page 31 and Table 11, "AMD DuronTM System Bus DC Characteristics," on page 34 IN Chapter 11, revised Figure 16, "OPN Example for the AMD DuronTM Processor Model 7" on page 75 Changes for the AMD DuronTM Processor Model 7 Data Sheet since October 2001 include the following: November 2001 F In Chapter 6, revised Table 1, "Thermal Design Power," on page 23 In Chapter 7, revised Table 6, "VCC_CORE AC and DC Characteristics," on page 28, revised Table 8, "VCC_CORE Voltage and Current," on page 31, revised Table 13, "General AC and DC Characteristics," on page 36, added new section, "Open Drain Test Circuit" on page 38, added Figure 11, "General ATE Open Drain Test Circuit" on page 38, added new section, "Thermal Protection Characterization" on page 40, and added Table 15, "Guidelines for Platform Thermal Protection of the Processor," on page 41 In Chapter 11, revised Figure 16, "OPN Example for the AMD DuronTM Processor Model 7" on page 75 Changes for the AMD DuronTM Processor Model 7 Data Sheet since September 2001 include the following: October 2001 E In Chapter 8, revised "Power-Up Timing Requirements" on page 44, and "Clock Multiplier Selection (FID[3:0])" on page 46 In Chapter 10, revised "FID[3:0] Pins" on page 70 Changes for the AMD DuronTM Processor Model 7 Data Sheet include the following: September 2001 D In Chapter 6, updated Table 1, "Thermal Design Power," on page 23 In Chapter 7, updated Table 8, "VCC_CORE Voltage and Current," on page 31 and revised Table 16, "APIC Pin AC and DC Characteristics," on page 41 In Chapter 11, updated Figure 16, "OPN Example for the AMD DuronTM Processor Model 7" on page 75 September 2001 C In Chapter 7, revised Figure 8, "VCC_CORE Voltage Waveform" on page 29 . August 2001 B Initial release of the AMD DuronTM Processor Model 7 Data Sheet. Revision History xi Preliminary Information AMD DuronTM Processor Model 7 Data Sheet xii 24310G--January 2002 Revision History Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 1 Overview The AMD DuronTM processor model 7 enables an optimized PC solution for value-conscious business and home users by providing the capability and flexibility to meet their computing needs for both today and tomorrow. The AMD Duron processor model 7 is the latest offering from AMD designed for the value segment of the market. The innovative design was developed to accommodate new and more advanced applications, meeting the requirements of today's most demanding value-conscious buyers without compromising their budget. Delivered in a CPGA package, the AMD Duron processor model 7 is the new AMD workhorse processor for value desktop systems, delivering an extremely high integer, floating-point, and 3-D multimedia performance for applications running on x86 system platforms. The AMD Duron processor model 7 provides value-conscious customers with access to advanced technology that allows their system investment to last for years to come. The AMD Duron processor model 7 is designed as a solid platform for surfing the Internet, digital entertainment, and personal creativity. In addition, it is engineered to enable superior business productivity by delivering an optimized combination of computing performance and value. The AMD Duron processor features a seventh-generation microarchitecture with an integrated, exclusive L2 cache, which supports the growing processor and system bandwidth requirements of emerging software, graphics, I/O, and memory technologies. The high-speed execution core of the AMD Duron processor includes multiple x86 instruction decoders, a dual-ported 128-Kbyte split level-one (L1) cache, an exclusive 64-Kbyte L2 cache, three independent integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of-order, three-way floating-point engine. The floating-point engine is capable of delivering outstanding performance on numerically complex applications. The AMD Duron processor model 7 microarchitecture i n c o r p o ra t e s 3 D N ow ! TM P ro f e s s i o n a l t e c h n o l o gy, a high-perfo rmance cache archit ect ure, and a 20 0-MHz, 1.6-Gigabyte per second system bus. The AMD Duron system Chapter 1 Overview 1 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 bus combines the latest technological advances, such as point-to-point topology, source-synchronous packet-based transfers, and low-voltage signaling to provide an extremely powerful, scalable bus for an x86 processor. The AMD Duron processor model 7 is binary-compatible with existing x86 software and backwards compatible with applications optimized for MMXTM and 3DNow! technology. Using a data format and Single-Instruction Multiple-Data (SIMD) operations based on the MMX instruction model, the AMD Duron processor can produce as many as four 32-bit, single-precision floating-point results per clock cycle. The 3 D N ow ! P rof e s s io n a l t ech n o logy im p le m e n t e d in t he A M D D u ro n p ro c e s s o r m o d e l 7 i n c l u d e s n ew i n t e g e r multimedia instructions and software-directed data movement instructions for optimizing such applications as digital content creation and streaming video for the Internet, as well as new instructions for Digital Signal Processing (DSP)/communications applications. 1.1 Microarchitecture Summary The following features summarize the AMD Duron processor model 7 microarchitecture: 2 An advanced nine-issue, superpipelined, superscalar x86 processor microarchitecture designed for high clock frequencies Multiple x86 instruction decoders Fully pipelined, floating-point unit that executes all x87 (floating-point), MMX and 3DNow! Professional technology instructions Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units A 72-entry instruction control unit Advanced dynamic branch prediction A 200-MHz AMD Duron system bus (scalable beyond 400 MHz) enabling leading-edge system bandwidth for data movement-intensive applications High-performance cache architecture featuring an integrated 128-Kbyte L1 cache and an exclusive 64-Kbyte L2 cache Overview Chapter 1 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 The A MD D u ro n p ro c e s so r d e l ive rs ex c e ll e n t s y s t e m performance in a cost-effective, industry-standard form factor. The AMD Duron processor is compatible with motherboards based on Socket A. Figure 1 shows a typical AMD Duron processor system block diagram. Thermal Monitor AMD DuronTM Processor Model 7 AMD Duron System Bus AGP AGP Bus Memory Bus System Controller (Northbridge) SDRAM or DDR PCI Bus Peripheral Bus Controller (Southbridge) LAN SCSI Modem / Audio LPC Bus USB Dual EIDE BIOS Figure 1. Typical AMD DuronTM Processor Model 7 System Block Diagram Chapter 1 Overview 3 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 4 24310G--January 2002 Overview Chapter 1 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 2 2.1 Interface Signals Overview The AMD DuronTM system bus architecture is designed to delive r excellent da ta movement bandwidth for nextgeneration x86 platforms as well as the high-performance required by enterprise-class application software. The system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 72-bit bidirectional data channel), source-synchronous clocking, and a packet-based protocol. In addition, the system bus supports several control, clock, and legacy signals. The interface signals use an impedance controlled push-pull, low-voltage, swing-signaling technology contained within the Socket A socket. For more information, see "AMD DuronTM System Bus Signals" on page 6, Chapter 10, "Pin Descriptions" on page 51, and the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. 2.2 Signaling Technology The AMD Duron system bus uses a low-voltage, swing-signaling technology, that has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. The signals are push-pull and impedance compensated. The signal inputs use differential receivers that require a reference voltage (VREF). The reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. Termination resistors are not needed because the driver is impedance-matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold. For more information about pins and signals, see Chapter 10, "Pin Descriptions" on page 51. Chapter 2 Interface Signals 5 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 2.3 24310G--January 2002 Push-Pull (PP) Drivers The AMD Duron processor model 7 supports Push-Pull (PP) drivers. The system logic configures the processor with the configuration parameter called SysPushPull (1=PP). The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins. See "ZN and ZP Pins" on page 74 for more information. 2.4 AMD DuronTM System Bus Signals The AMD Duron system bus is a clock-forwarded, point-to-point interface with the following three point-to-point channels: A 13-bit unidirectional output address/command channel A 13-bit unidirectional input address/command channel A 72-bit bidirectional data channel For more information, see Chapter 7, "Electrical Data" on page 25 and the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. 6 Interface Signals Chapter 2 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor. This diagram shows the logical grouping of the input and output signals. Clock SYSCLK Data Probe/SysCMD Request Power Management and Initialization SYSCLK# SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SDATAINVALID# SDATAOUTVALID# SFILLVALID# SADDIN[14:2]# SADDINCLK# VID[4:0] COREFB COREFB# PWROK FID[3:0] AMD DuronTM Processor Model 7 SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET# FERR IGNNE# INIT# INTR NMI A20M# SMI# FLUSH# THERMDA THERMDC PICCLK PICD[1:0] Voltage Control Frequency Control Legacy Thermal Diode APIC Figure 2. Logic Symbol Diagram Chapter 3 Logic Symbol Diagram 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 8 Logic Symbol Diagram 24310G--January 2002 Chapter 3 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 4 Power Management This chapter describes the power management control system o f t h e A M D D u r o n TM p ro c e s s o r m o d e l 7 . T h e p o we r management features of the processor are compliant with the ACPI 1.0b and ACPI 2.0 specifications. 4.1 Power Management States The AMD Duron processor model 7 supports low-power Halt and Stop Grant states. These states are used by Advanced Configuration and Power Interface (ACPI) enabled operating systems for processor power management. Figure 3 shows the power management states of the processor. The figure includes the ACPI "Cx" naming convention for these states. Execute HLT C1 Halt C0 Working4 SMI#, INTR, NMI, INIT#, RESET# Probe Serviced STPCLK# deasserted Incoming Probe STPCLK# asserted PC LK #d ST ea PC sse LK rte #a d3 sse rte d2 (Read PLVL2 register or throttling) Probe Serviced Incoming Probe Probe State1 ST C2 Stop Grant Cache Snoopable ST ST PC LK # PC LK # ass e de ass ert ed rte d S1 Stop Grant Cache Not Snoopable Sleep Legend Hardware transitions Software transitions Note: The AMD DuronTM System Bus is connected during the following states: 1) The Probe state 2) During transitions between the Halt state and the C2 Stop Grant state 3) During transitions between the C2 Stop Grant state and the Halt state 4) C0 Working state Figure 3. AMD DuronTM Processor Model 7 Power Management States Chapter 4 Power Management 9 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 The following sections provide an overview of the power m a n a g e m e n t s t a t e s . Fo r m o re d e t a i l s , re f e r t o t h e AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. Note: In all power management states that the processor is powered, the system must not stop the system clock (SYSCLK/SYSCLK#) to the processor. Working State The Working state is the state in which the processor is executing instructions. Halt State When the processor executes the HLT instruction, the processor enters the Halt state and issues a Halt special cycle to the AMD Duron system bus. The processor only enters the low power state dictated by the CLK_Ctl MSR if the system controller (Northbridge) disconnects the AMD Duron system bus in response to the Halt special cycle. If STPCLK# is asserted, the processor will exit the Halt state and enter the Stop Grant state. The processor will initiate a system bus connect, if it is disconnected, then issue a Stop Grant special cycle. When STPCLK# is deasserted, the processor will exit the Stop Grant state and re-enter the Halt state. The processor will issue a Halt special cycle when re-entering the Halt state. The Halt state is exited when the processor detects the assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR or NMI pins, or via a local APIC interrupt message. When the Halt state is exited, the processor will initiate an AMD Duron system bus connect if it is disconnected. Stop Grant States 10 The processor enters the Stop Grant state upon recognition of assertion of STPCLK# input. After entering the Stop Grant state, the processor issues a Stop Grant special bus cycle on the AMD Duron system bus. The processor is not in a low-power state at this time, because the AMD Duron system bus is still connected. After the Northbridge disconnects the AMD Duron system bus in response to the Stop Grant special bus cycle, the processor enters a low-power state dictated by the CLK_Ctl MSR. If the Northbridge needs to probe the processor during the Stop Grant state while the system bus is disconnected, it Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 must first connect the system bus. Connecting the system bus places the processor into the higher power probe state. After the Northbridge has completed all probes of the processor, the Northbridge must disconnect the AMD Duron system bus again so that the processor can return to the low-power state. During the Stop Grant states, the processor latches INIT#, INTR, NMI, SMI#, or a local APIC interrupt message, if they are asserted. The Stop Grant state is exited upon the deassertion of STPCLK# or the assertion of RESET#. When STPCLK# is deasserted, the processor initiates a connect of the AMD Duron system bus if it is disconnected. After the processor enters the Working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where STPCLK# was initially recognized. If RESET# is sampled asserted during the Stop Grant state, the processor exits the Stop Grant state and the reset process begins. There are two mechanisms for asserting STPCLK#--hardware and software. The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. This is accomplished by asserting the THERM# input to the Southbridge. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until THERM# is deasserted. Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. The operating system places the processor into the C2 Stop Grant state by reading the P_LVL2 register in the Southbridge. If an ACPI Thermal Zone is defined for the processor, the operating system can initiate throttling with STPCLK# using the ACPI defined P_CNT register in the Southbridge. The Northbridge connects the AMD Duron system bus, and the processor enters the Probe state to service cache snoops during Stop Grant for C2 or throttling. In C2, probes are allowed, as shown in Figure 3 on page 9 Chapter 4 Power Management 11 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 The Stop Grant state is also entered for the S1, Powered On Suspend, system sleep state based on a write to the SLP_TYP and SLP_EN fields in the ACPI-defined Power Management 1 control register in the Southbridge. During the S1 Sleep state, system software ensures no bus master or probe activity occurs. The Southbridge deasserts STPCLK# and brings the processor out of the S1 Stop Grant state when any enabled resume event occurs. Probe State 12 The Probe state is entered when the Northbridge connects the AMD Duron system bus to probe the processor (for example, to snoop the processor caches) when the processor is in the Halt or Stop Grant state. When in the Probe state, the processor responds to a probe cycle in the same manner as when it is in the Working state. When the probe has been serviced, the processor returns to the same state as when it entered the Probe state (Halt or Stop Grant state). When probe activity is completed the processor only returns to a low-power state after the Northbridge disconnects the AMD Duron system bus again. Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 4.2 Connect and Disconnect Protocol Significant power savings of the processor only occur if the proc essor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state. The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle. The option of disconnecting is controlled by an enable bit in the Northbridge. If the Northbridge requires the processor to service a probe after the system bus has been disconnected, it must first initiate a system bus connect. Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop Grant special cycles, the AMD Duron system bus connect protocol includes the CONNECT, PROCRDY, and CLKFWDRST signals and a Connect special cycle. AMD Duron system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant. Reconnect is initiated by the processor in response to an interrupt for Halt or STPCLK# deassertion. Reconnect is initiated by the Northbridge to probe the processor. The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles. When the Northbridge receives the Halt or Stop Grant special cycle from the processor and, if there are no outstanding probes or data movements, the Northbridge deasserts CONNECT a minimum of eight SYSCLK periods after the last command sent to the processor. The processor detects the deassertion of CONNECT on a rising edge of SYSCLK and deasserts PROCRDY to the Northbridge. In return, the Northbridge asserts CLKFWDRST in anticipation of reestablishing a connection at some later point. Note: The Northbridge must disconnect the processor from the AMD Duron system bus before issuing the Stop Grant special cycle to the PCI bus or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransportTM technology. This note applies to current chipset implementation-- alternate chipset implementations that do not require this are possible. Chapter 4 Power Management 13 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Note: In response to Halt special cycles, the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately. The processor can receive an interrupt after it sends a Halt special cycle, or STPCLK# deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs. In this case, the processor sends the Connect special cycle to the Northbridge, rather than continuing with the disconnect sequence. In response to the Connect special cycle, the Northbridge cancels the disconnect request. The system is required to assert the CONNECT signal before returning the C-bit for the connect special cycle (assuming CONNECT has been deasserted). For more information, see the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for the definition of the C-bit and the Connect special cycle. 14 Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Figure 4 shows STPCLK# assertion resulting in the processor in t h e S t o p G ra n t st a t e a n d t he A M D D uron s ys t e m b us disconnected. STPCLK# AMD DuronTM System Bus Stop Grant CONNECT PROCRDY CLKFWDRST Stop Grant PCI Bus Figure 4. AMD DuronTM System Bus Disconnect Sequence in the Stop Grant State An example of the AMD Duron system bus disconnect sequence is as follows: 1. The peripheral controller (Southbridge) asserts STPCLK# to place the processor in the Stop Grant state. 2. When the processor recognizes STPCLK# asserted, it enters the Stop Grant state and then issues a Stop Grant special cycle. 3. When the special cycle is received by the Northbridge, it deasserts CONNECT, assuming no probes are pending, initiating a bus disconnect to the processor. 4. The processor responds to the Northbridge by deasserting PROCRDY. 5. The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence. 6. After the processor is disconnected from the bus, the processor enters a low-power state. The Northbridge passes the Stop Grant special cycle along to the Southbridge. Chapter 4 Power Management 15 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state, connects the processor to the AMD Duron system bus, and puts the processor into the Working state. STPCLK# PROCRDY CONNECT CLKFWDRST Figure 5. Exiting the Stop Grant State and Bus Connect Sequence The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus: 1. The Southbridge deasserts processor of a wake event. STPCLK#, informing the 2. When the processor recognizes STPCLK# deassertion, it exits the low-power state and asserts PROCRDY, notifying the Northbridge to connect to the bus. 3. The Northbridge asserts CONNECT. 4. The Northbridge deasserts CLKFWDRST, synchronizing the forwarded clocks between the processor and the Northbridge. 5. The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution. 16 Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Connect State Diagram Figure 6 below and Figure 7 on page 18 show the Northbridge and processor connect state diagrams, respectively. 4/A 1 2/A Disconnect Pending Disconnect Requested Connect 3 3/C 5/B 8 8 Reconnect Pending Disconnect Probe Pending 2 7/D,C 6/C 7/D Probe Pending 1 Condition Action 1 A disconnect is requested and probes are still pending. 2 A disconnect is requested and no probes are pending. A Deassert CONNECT eight SYSCLK periods after last SysDC sent. 3 A Connect special cycle from the processor. B Assert CLKFWDRST. 4 No probes are pending. C Assert CONNECT. 5 PROCRDY is deasserted. D Deassert CLKFWDRST. 6 A probe needs service. 7 PROCRDY is asserted. Three SYSCLK periods after CLKFWDRST is deasserted. Although reconnected to the system interface, the 8 Northbridge must not issue any non-NOP SysDC commands for a minimum of four SYSCLK periods after deasserting CLKFWDRST. Figure 6. Northbridge Connect State Diagram Chapter 4 Power Management 17 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Connect 6/B 1 2/B Connect Pending 2 Disconnect Pending 5 Connect Pending 1 3/A Disconnect 4/C Condition 1 Action CONNECT is deasserted by the Northbridge (for a previously sent Halt or Stop Grant special cycle). Processor receives a wake-up event and must cancel 2 the disconnect request. 3 Deassert PROCRDY and slow down internal clocks. 4 Processor wake-up event or CONNECT asserted by Northbridge. A CLKFWDRST is asserted by the Northbridge. B Issue a Connect special cycle.* C Return internal clocks to full speed and assert PROCRDY. Note: * 5 CLKFWDRST is deasserted by the Northbridge. 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted. The Connect special cycle is only issued after a processor wake-up event (interrupt or STPCLK# deassertion) occurs. If the AMD DuronTM system bus is connected so the Northbridge can probe the processor, a Connect special cycle is not issued at that time (it is only issued after a subsequent processor wake-up event). Figure 7. Processor Connect State Diagram 18 Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 4.3 Clock Control The processor implements a Clock Control (CLK_Ctl) MSR (address C001_001Bh) that determines the internal clock divisor when the AMD Duron system bus is disconnected. Refer to the AMD AthlonTM and AMD DuronTM Processors BIOS, Software, and Debug Developers Guide, order# 21656, for more details on the CLK_Ctl register. Chapter 4 Power Management 19 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 20 24310G--January 2002 Power Management Chapter 4 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 5 CPUID Support AMD DuronTM processor model 7 version and feature set recognition can be performed through the use of the CPUID instruction, that provides complete information about the processor--vendor, type, name, etc., and its capabilities. Software can make use of this information to accurately tune the system for maximum performance and benefit to users. For information on the use of the CPUID instruction see the following documents: Chapter 5 AMD Processor Recognition Application Note, order# 20734 AMD AthlonTM Processor Recognition Application Note Addendum, order# 21922 AMD AthlonTM and AMD DuronTM Processors BIOS, Software, and Debug Developers Guide, order# 21656 CPUID Support 21 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 22 24310G--January 2002 CPUID Support Chapter 5 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 6 Thermal Design The AMD DuronTM processor model 7 provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor. The diode anode (THERMDA) and cathode (THERMDC) are available as pins on the processor. Refer to "THERMDA and THERMDC Pins" on page 73 for more details. For information about thermal design for the AMD Duron processor model 7, including layout and airflow considerations, see the AMD AthlonTM Processor Thermal, Mechanical, and Chassis Cooling Design Guide, order# 23794, and the cooling guidelines on http://www.amd.com. Table 1 shows the thermal design power specifications for the AMD Duron processor model 7. Table 1. Thermal Design Power Frequency (MHz) Nominal Voltage Maximum Thermal Typical Thermal Max Die Power Power Temperature 900 42.7 W 39.2 W 950 44.4 W 40.8 W 46.1 W 42.4 W 1100 50.3 W 46.2 W 1200 54.7 W 50.3 W 1300 60.0 W 55.2 W 1000 1.75 V 90C Note: The thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal VCC_CORE. Thermal solutions must monitor the processor temperature to prevent the processor from exceeding its maximum die temperature. Chapter 6 Thermal Design 23 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24 24310G--January 2002 Thermal Design Chapter 6 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 7 Electrical Data 7.1 Conventions The conventions used in this chapter are as follows: 7.2 Current specified as being sourced by the processor is negative. Current specified as being sunk by the processor is positive. Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group. Table 2 defines each group and the signals contained in each group. Table 2. Interface Signal Groupings Signal Group Signals Notes Power VID[4:0], VCCA, VCC_CORE, COREFB, COREFB# See "Absolute Ratings" on page 30, "Voltage Identification (VID[4:0])" on page 26, "VID[4:0] Pins" on page 73, "" on page 27,"VCCA Pin" on page 73, and "COREFB and COREFB# Pins" on page 69. Frequency FID[3:0] See "Frequency Identification (FID[3:0])" on page 27 and "FID[3:0] Pins" on page 70. SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK See Table 9, "SYSCLK and SYSCLK# DC Characteristics," on page 32, Table 10, "SYSCLK and SYSCLK# AC Characteristics," on page 33, "SYSCLK and SYSCLK#" on page 73, and "PLL Bypass and Test Pins" on page 72. System Clocks SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, See "AMD DuronTM System Bus AC AMD DuronTM SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, and DC Characteristics" on page 34, System Bus SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, and "CLKFWDRST Pin" on page 68. CONNECT Chapter 7 Electrical Data 25 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet Table 2. 24310G--January 2002 Interface Signal Groupings (continued) Signal Group Signals Notes Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH# See "General AC and DC Characteristics" on page 36, "INTR Pin" on page 71, "NMI Pin" on page 72, "SMI# Pin" on page 72, "INIT# Pin" on page 71, "A20M# Pin" on page 68, "FERR Pin" on page 69,"IGNNE# Pin" on page 71, "SYSCLK and SYSCLK#" on page 73, and "FLUSH# Pin" on page 71. JTAG TMS, TCK, TRST#, TDI, TDO See "General AC and DC Characteristics" on page 36. PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG See "General AC and DC Characteristics" on page 36, "PLL Bypass and Test Pins" on page 72, "Scan Pins" on page 72, "Analog Pin" on page 68. Test Miscellaneous DBREQ#, DBRDY, PWROK See "General AC and DC Characteristics" on page 36, "DBRDY and DBREQ# Pins" on page 69, "PWROK Pin" on page 72. APIC PICD[1:0]#, PICCLK See "APIC Pins AC and DC Characteristics" on page 41, and "APIC Pins, PICCLK, PICD[1:0]#" on page 68. THERMDA, THERMDC Table 14, "Thermal Diode Electrical Characteristics," on page 39, and "THERMDA and THERMDC Pins" on page 73 Thermal 7.3 Voltage Identification (VID[4:0]) Table 3 shows the VID[4:0] DC Characteristics. For more information on VID[4:0] DC Characteristics, see "VID[4:0] Pins" on page 73. Table 3. Parameter VID[4:0] DC Characteristics Description Min IOL Output Current Low 16 mA VOH Output High Voltage - Max 2.625 V* Note: * 26 The VID pins must not be pulled above this voltage by an external pullup resistor. Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 7.4 Frequency Identification (FID[3:0]) Table 4 shows the FID[3:0] DC characteristics. For more information, see "FID[3:0] Pins" on page 70. Table 4. FID[3:0] DC Characteristics Parameter Description Min IOL Output Current Low 16 mA VOH Output High Voltage - Max 2.625 V * Note: * 7.5 The FID pins must not be pulled above this voltage by an external pullup resistor. VCCA AC and DC Characteristics Table 5 shows the AC and DC characteristics for VCCA. For more information, see "VCCA Pin" on page 73. Table 5. Symbol VCCA AC and DC Characteristics Parameter Min Nominal Max Units Notes 2.5 2.75 V 1 50 mA/GHz 2 VVCCA VCCA Pin Voltage 2.25 IVCCA VCCA Pin Current 0 Notes: 1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted. 2. Measured at 2.5 V. 7.6 Decoupling See the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363, or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD DuronTM processor model 7. Chapter 7 Electrical Data 27 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.7 24310G--January 2002 VCC_CORE Characteristics Table 6 shows the AC and DC characteristics for VCC_CORE. Th e V C C _ C O R E n o m i n a l va l u e i s s h ow n i n Ta b l e 8 , "VCC_CORE Voltage and Current," on page 31. See Figure 8 on page 29 for a graphical representation of the VCC_CORE waveform. Table 6. VCC_CORE AC and DC Characteristics Symbol Parameter Limit in Working State Units VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM* 50 mV VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM* -50 mV VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM* 150 mV VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM* -100 mV tMAX_AC Maximum excursion time for AC transients 10 s tMIN_AC Negative excursion time for AC transients 5 s Note: *All voltage measurements are taken differentially 28 at the COREFB/COREFB# pins. Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Figure 8 shows the processor core voltage (VCC_CORE) waveform response to perturbation. The tMIN_AC (negative AC transient excursion time) and tMAX_AC (positive AC transient excursion time) represent the maximum allowable time below or above the DC tolerance thresholds. tmax_AC VCC_CORE_MAX_AC VCC_CORE_MAX_DC VCC_CORE_NOM VCC_CORE_MIN_DC VCC_CORE_MIN_AC tmin_AC ICORE_MAX dI /dt ICORE_MIN Figure 8. VCC_CORE Voltage Waveform Chapter 7 Electrical Data 29 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.8 24310G--January 2002 Absolute Ratings The AMD Duron processor model 7 should not be subjected to conditions exceeding the absolute ratings, as such conditions can adversely affect long-term reliability or result in functional damage. Table 7 lists the maximum absolute ratings of operation for the AMD Duron processor. Table 7. Absolute Ratings Parameter Description Min Max VCC_CORE AMD DuronTM Processor Model 7 core supply -0.5 V VCC_CORE Max + 0.5 V VCCA AMD Duron Processor Model 7 PLL supply -0.5 V VCCA Max + 0.5 V VPIN Voltage on any signal pin -0.5 V VCC_CORE Max + 0.5 V TSTORAGE Storage temperature of processor -40C 100C 30 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 7.9 VCC_CORE Voltage and Current Table 8 shows the voltage and current for the AMD Duron processor model 7 during normal and reduced power states. Table 8. VCC_CORE Voltage and Current Frequency (MHz) Nominal Voltage Die Temperature ICC (Processor Current) Typical Max 900 22.4 A 24.4 A 950 23.3 A 25.4 A 24.2 A 26.3 A 1100 26.4 A 28.7 A 1200 28.7 A 31.3 A 1300 31.5 A 34.3 A 0.66 A 1.54 A 1000 1.75 Stop Grant S1 or Sleep State1, 2, 3, 4, 5 1.30 V 90C 50C Notes: 1. The cooling fan can be turned off during the Sleep State, but customers should test their systems in Sleep state to ensure that the system, when using typical parts, has adequate cooling (without the fan during the Sleep State) to meet the temperature specification of the product. 2. See Figure 3, "AMD DuronTM Processor Model 7 Power Management States" on page 9. 3. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified current. 4. These currents occur when the AMD DuronTM System Bus is disconnected and a low power ratio of 1/64 is applied to the core clock grid of the processor as dictated by a value of 6003_D22Fh programmed into the Clock Control (CLK_Ctl) MSR. 5. The Stop Grant current consumption is characterized and not tested. Chapter 7 Electrical Data 31 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.10 24310G--January 2002 SYSCLK and SYSCLK# AC and DC Characteristics Table 9 shows the DC characteristics of the SYSCLK and SYSCLK# differential clocks. The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK# signal represents CLKIN# and RSTCLK# tied together. Table 9. SYSCLK and SYSCLK# DC Characteristics Symbol Description Min Max Units VThreshold-DC Crossing before transition is detected (DC) 400 mV VThreshold-AC Crossing before transition is detected (AC) 450 mV -1 mA ILEAK_P Leakage current through P-channel pullup to VCC_CORE ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) VCROSS Differential signal crossover CPIN Capacitance* 1 mA VCC_CORE/2100 mV 12* pF 4 Note: * The following processor inputs have twice the listed capacitance because they connect to two input pads--SYSCLK and SYSCLK#. SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#. Figure 9 shows the DC characteristics of the SYSCLK and SYSCLK# signals. VCROSS VThreshold-DC = 400mV VThreshold-AC = 450mV Figure 9. SYSCLK and SYSCLK# Differential Clock Signals 32 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 10 shows the SYSCLK/SYSCLK# differential clock AC characteristics of the AMD Duron processor model 7. Table 10. SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Minimum Maximum Units 50 100 MHz 30% 70% - Clock Frequency Duty Cycle t1 Period 10 ns t2 High Time 1.8 ns t3 Low Time 1.8 ns t4 Fall Time 2.0 ns t5 Rise Time 2.0 ns 300 ps Period Stability Notes 1, 2 Notes: 1. Circuitry driving the AMD DuronTM system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter. The -20dB attenuation point, as measured into a 10- or 20-pF load must be less than 500 kHz. 2. Circuitry driving the AMD Duron system bus clock inputs may purposely alter the AMD Duron system bus clock frequency (spread spectrum clock generators). In no cases can the AMD Duron system bus period violate the minimum specification above. AMD Duron system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 kHz. Figure 10 shows a sample waveform of the SYSCLK signal. t2 VThreshold-AC VCROSS t3 t4 t5 t1 Figure 10. SYSCLK Waveform Chapter 7 Electrical Data 33 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.11 24310G--January 2002 AMD DuronTM System Bus AC and DC Characteristics Table 11 shows the DC characteristics of the AMD Duron system bus used by the AMD Duron processor model 7. See Table 6, "VCC_CORE AC and DC Characteristics," on page 28 for information on TDIE and VCC_CORE. For information about SYSCLK and SYSCLK#, see "SYSCLK and SYSCLK#" on page 73 and Table 19, "Pin Name Abbreviations," on page 54. Table 11. AMD DuronTM System Bus DC Characteristics Symbol VREF Parameter Condition Min Max (0.5*VCC_CORE) (0.5*VCC_CORE) -50 +50 DC Input Reference Voltage IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal Units Notes mV 1 A -200 100 A VIH Input High Voltage VREF + 200 VCC_CORE + 500 mV VIL Input Low Voltage -500 VREF - 200 mV VOH Output High Voltage IOUT = -200 A 0.85 VCC_CORE VCC_CORE+500 mV 2 VOL Output Low Voltage IOUT = 1 mA -500 400 mV 2 ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) -1 ILEAK_N Tristate Leakage Pulldown CIN Input Pin Capacitance VIN = VCC_CORE Nominal 4 mA 1 mA 12 pF Notes: 1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed above. 2. Specified at the T DI E an d V C C _ C O R E s pe ci f i ca ti o ns i n t hi s do cu m e n t. 34 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 The AC characteristics of the AMD Duron system bus are shown in Table 12 on page 35. The parameters are grouped based on the source or destination of the signals involved. Table 12. AMD DuronTM System Bus AC Characteristics Group All Signals Forward Clocks Sync Symbol Parameter Min Max Units Notes TRISE Output Rise Slew Rate 1 3 V/ns 1 TFALL Output Fall Slew Rate 1 3 V/ns 1 TSKEW-SAMEEDGE Output skew with respect to the same clock edge - 385 ps 2 TSKEW-DIFFEDGE Output skew with respect to a different clock edge - 770 ps 2 TSU Input Data Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input Clocks 4 12 pF COUT Capacitance on output Clocks 4 12 pF TVAL RSTCLK to Output Valid 250 2000 ps 4, 5 TSU Setup to RSTCLK 500 ps 4, 6 THD Hold from RSTCLK 1000 ps 4, 6 Notes: 1. Rise and fall time ranges are guidelines over which the I/O has been characterized. 2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock. 4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST. 5. T VAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF. 6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of RSTCLK. Chapter 7 Electrical Data 35 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.12 24310G--January 2002 General AC and DC Characteristics Table 13 shows the AMD Duron processor model 7 AC and DC ch a ra c t e r i s t i c s o f t h e S o u t h b r i d g e , J TAG , t e s t , a n d miscellaneous pins. Table 13. General AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes VIH Input High Voltage (VCC_CORE/2) + 200 mV VCC_CORE + 300 mV V 1, 2 VIL Input Low Voltage -300 350 mV 1, 2 VOH Output High Voltage VCC_CORE - 400 VCC_CORE + 300 mV VOL Output Low Voltage -300 400 mV ILEAK_P Tristate Leakage Pullup ILEAK_N Tristate Leakage Pulldown IOH Output High Current IOL Output Low Current TSU VIN = VSS (Ground) -1 VIN = VCC_CORE Nominal mA 600 A -16 mA 3 16 mA 3 Sync Input Setup Time 2.0 ns 4, 5 THD Sync Input Hold Time 0.0 ps 4, 5 TDELAY Output Delay with respect to RSTCLK 0.0 ns 5 6.1 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Characterized across DC supply voltage range. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE minimum and VCC_CORE maximum. IOL and IOH are measured at VOL max and VOH min, respectively. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. These are aggregate numbers. Edge rates indicate the range over which inputs were characterized. In asynchronous operation, the signal must persist for this time to enable capture. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST. The approximate value for standard case in normal mode operation. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency. Reassertions of the signal within this time are not guaranteed to be seen by the core. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations. 14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, "Power-Up Timing Requirements," for more information. 36 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 13. General AC and DC Characteristics (continued) Symbol Parameter Description Condition Min Max Units Notes TBIT Input Time to Acquire 20.0 ns 7, 8 TRPT Input Time to Reacquire 40.0 ns 9-13 TRISE Signal Rise Time 1.0 3.0 V/ns 6 TFALL Signal Fall Time 1.0 3.0 V/ns 6 CPIN Pin Capacitance 4 12 pF T VALID Time to data valid 100 ns 14 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Characterized across DC supply voltage range. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE minimum and VCC_CORE maximum. IOL and IOH are measured at VOL max and VOH min, respectively. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. These are aggregate numbers. Edge rates indicate the range over which inputs were characterized. In asynchronous operation, the signal must persist for this time to enable capture. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST. The approximate value for standard case in normal mode operation. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency. Reassertions of the signal within this time are not guaranteed to be seen by the core. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations. 14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, "Power-Up Timing Requirements," for more information. Chapter 7 Electrical Data 37 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 7.13 24310G--January 2002 Open Drain Test Circuit Figure 11 is a test circuit that may be used on Automated Test Equipment (ATE) to test for validity on open drain pins. Refer to Table 13, "General AC and DC Characteristics," on page 36 for timing requirements. VTermination1 50 3% Open Drain Pin IOL = Output Current2 Notes: 1. VTermination = 1.2 V for VID and FID pins VTermination = 1.0 V for APIC pins 2. IOL = -16 mA for VID and FID pins IOL = -12 mA for APIC pins Figure 11. General ATE Open Drain Test Circuit 38 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 7.14 Thermal Diode Characteristics Thermal Diode Electrical Characteristics. Table 14 shows the AMD Duron processor model 7 electrical characteristics of the on-die thermal diode. Table 14. Thermal Diode Electrical Characteristics Symbol Parameter Description Min Ifw Forward bias current 5 n Diode ideality factor 1.002 Nom 1.008 Max Units Notes 300 A 1 1.016 2, 3, 4, 5 Notes: 1. 2. 3. 4. The sourcing current should always be used in forward bias only. Characterized at 95C with a forward bias current pair of 10 A and 100 A. Not 100% tested. Specified by design and limited characterization. The diode ideality factor, n, is a correction factor to the ideal diode equation. For the following equations, use the following variables and constants: n Diode ideality factor k Boltzmann constant q Electron charge constant T Diode temperature (Kelvin) VBE Voltage from base to emitter Collector current IC Saturation current IS N Ratio of collector currents The equation for VBE is: IC nkT V BE = --------- ln ae -----o e IS o q By sourcing two currents and using the above equation, a difference in base emitter voltage can be found that leads to the following equation for temperature: V BE T = ---------------------------k n ln ( N ) --q 5. If a different sourcing current pair is used other than 10 A and 100 A, the following equation should be used to correct the temperature. Subtract this offset from the temperature measured by the temperature sensor. For the following equations, use the following variables and constants: Ihigh High sourcing current Ilow Low sourcing current Toffset (in C) can be found using the following equation: ( I high - I low ) 4 T offset = ( 6.0 10 ) -------------------------------- - 2.34 I high ln ae -----------o e I low o Chapter 7 Electrical Data 39 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Thermal Protection Characterization. The following section describes parameters relating to thermal protection. The implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement. Thermal limits in motherboard design are necessary to protect the processor from thermal damage. T S HU TD OW N is the temperature for thermal protection circuitry to initiate shutdown of the processor. T SD_DELAY is the maximum time allowed from the detection of the over-temperature condition to processor shutdown to prevent thermal damage to the processor. Systems that do not implement thermal protection circuitry or that do not react within the time specified by TSD_DELAY can cause thermal damage to the processor during the unlikely events of fan failure or powering up the processor without a heat-sink. The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. Thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents: AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363 Thermal Diode Monitoring Circuits, order# 25658 AMD Thermal, Mechanical, and Chassis Cooling Design Guide, order# 23794 http://www1.amd.com/products/athlon/thermals Table 15 on page 41 shows the T SHUTDOWN and T SD_DELAY specifications for circuitry in motherboard design necessary for thermal protection of the processor. 40 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 15. Guidelines for Platform Thermal Protection of the Processor Symbol Parameter Description Max Units Notes TSHUTDOWN Thermal diode shutdown temperature for processor protection 125 C 1, 2, 3 TSD_DELAY 500 ms 1, 3 Maximum allowed time from TSHUTDOWN detection to processor shutdown Notes: 1. The thermal diode is not 100% tested, it is specified by design and limited characterization. 2. The thermal diode is capable of responding to thermal events of 40C/s or faster. 3. The AMD DuronTM processor model 7 provides a thermal diode for measuring die temperature of the processor. The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. Refer to Thermal Diode Monitoring Circuits, order# 25658, for thermal protection circuitry designs. 7.15 APIC Pins AC and DC Characteristics Table 16 shows the AMD Duron processor model 7 AC and DC characteristics of the APIC pins. Table 16. APIC Pin AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes VIH Input High Voltage 1.7 2.625 V 1, 3 VIL Input Low Voltage -300 700 mV 1, 2 VOH Output High Voltage 2.625 V 3 VOL Output Low Voltage 400 mV ILEAK_P Tristate Leakage Pullup ILEAK_N Tristate Leakage Pulldown IOL Output Low Current TRISE Signal Rise Time 1.0 3.0 V/ns 4 TFALL Signal Fall Time 1.0 3.0 V/ns 4 CPIN Pin Capacitance 4 12 pF -300 VIN = VSS (Ground) -1 VIN = 2.5 V VOL Max mA 1 12 mA mA Notes: 1. Characterized across DC supply voltage range 2. 2.625 V = 2.5 V + 5% maximum 3. Edge rates indicate the range over which inputs were characterized Chapter 7 Electrical Data 41 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 42 24310G--January 2002 Electrical Data Chapter 7 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 8 Signal and Power-Up Requirements The AMD DuronTM processor model 7 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges. 8.1 Power-Up Requirements Signal Sequence and Timing Description Figure 12 shows the relationship between key signals in the system during a power-up sequence. This figure details the requirements of the processor. 3.3 V Supply VCCA (2.5 V) (for PLL) VCC_CORE (Processor Core) 2 1 RESET# Warm reset condition 6 4 NB_RESET# 5 PWROK 7 8 FID[3:0] 3 System Clock Figure 12. Signal Relationship Requirements During Power-Up Sequence Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. 2. Requirements 1-8 in Figure 12 are described in "Power-Up Timing Requirements" on page 44. Chapter 8 Signal and Power-Up Requirements 43 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Power-Up Timing Requirements. The signal timing requirements are as follows: 1. RESET# must be asserted before PWROK is asserted. The AMD Duron processor model 7 does not set the correct clock multiplier if PWROK is asserted prior to a RESET# assertion. It is recommended that RESET# be asserted at least 10 nanoseconds prior to the assertion of PWROK. In practice, a Southbridge asserts RESET# milliseconds before PWROK is deasserted. 2. All motherboard voltage planes must be within specification before PWROK is asserted. PWROK is an output of the voltage regulation circuit on the motherboard. PWROK indicates that VCC_CORE and all other voltage planes in the system are within specification. The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3.3 V supply being within specification. This delay ensures that the system clock (SYSCLK/SYSCLK#) is operating within specification when PWROK is asserted. The processor core voltage, VCC_CORE, must be within specification as dictated by the VID[4:0] pins driven by the processor before PWROK is asserted. Before PWROK assertion, the AMD Duron processor is clocked by a ring oscillator. The processor PLL is powered by VCCA. The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted. VCCA must be within specification at least five microseconds before PWROK is asserted. In practice VCCA, VCC_CORE, and all other voltage planes must be within specification for several milliseconds before PWROK is asserted. After PWROK is asserted, the processor PLL locks to its operational frequency. 3. The system clock (SYSCLK/SYSCLK#) must be running before PWROK is asserted. When PWROK is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL. The reference system 44 Signal and Power-Up Requirements Chapter 8 Preliminary Information 24310G--January 2002 AMD DuronTM Processor Model 7 Data Sheet clock must be valid at this time. The system clocks are designed to be running after 3.3 V has been within specification for three milliseconds. 4. PWROK assertion to deassertion of RESET# The duration of RESET# assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1 ns phase error. The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL. The PLL lock time may take from hundreds of nanoseconds to tens of microseconds. It is recommended that the minimum time between PWROK assertion to the deassertion of RESET# be at least 1.0 milliseconds. Southbridges enforce a delay of 1.5 to 2.0 milliseconds between PWRGD (Southbridge version of PWROK) assertion and NB_RESET# deassertion. 5. PWROK must be monotonic and meet the timing requirements as defined in Table 13, "General AC and DC Characteristics," on page 36. The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK. 6. NB_RESET# must be asserted (causing CONNECT to also assert) before RESET# is deasserted. In practice all Southbridges enforce this requirement. If NB_RESET# does not assert until after RESET# has deasserted, the processor misinterprets the CONNECT assertion (due to NB_RESET# being asserted) as the beginning of the SIP transfer. There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor before RESET# is deasserted. 7. The FID[3:0] signals are valid within 100 ns after PWROK is asserted. The chipset must not sample the FID[3:0] signals until they become valid. Refer to the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363, for the specific implementation and additional circuitry required. 8. The FID[3:0] signals become valid within 100 ns after RESET# is asserted. Refer to the AMD AthlonTM ProcessorBased Motherboard Design Guide, order# 24363, for the specific implementation and additional circuitry required. Chapter 8 Signal and Power-Up Requirements 45 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet Clock Multiplier Selection (FID[3:0]) 24310G--January 2002 The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to determine the correct Serial Initialization Packet (SIP). The chipset then sends the SIP information to the processor for configuration of the AMD Duron system bus for the clock multiplier that determines the processor frequency indicated by the FID[3:0] code. The SIP is sent to the processor using the SIP protocol. This protocol uses the PROCRDY, CONNECT, and CLKFWDRST signals, that are synchronous to SYSCLK. For more information, see "FID[3:0] Pins" on page 70. Serial Initialization Packet (SIP) Protocol. Refer to AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for details of the SIP protocol. 8.2 Processor Warm Reset Requirements Northbridge Reset Pins 46 RESET# cannot be asserted to the processor without also being asserted to the Northbridge. RESET# to the Northbridge is the same as PCI RESET#. The minimum assertion for PCI RESET# is one millisecond. Southbridges enforce a minimum assertion of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0 milliseconds. Signal and Power-Up Requirements Chapter 8 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 9 9.1 Mechanical Data Introduction The AMD D uronTM proces sor model 7 connects to the motherboard through a Pin Grid Array (PGA) socket named Socket A and utilizes the Ceramic Pin Grid Array (CPGA) package type described in "CPGA Package Description" on page 48. For more information, see the AMD AthlonTM ProcessorBased Motherboard Design Guide, order# 24363. 9.2 Die Loading The processor die on the CPGA package is exposed at the top of the package. This feature facilitates heat transfer from the die to an approved heat sink. It is critical that the mechanical loading of the heat sink does not exceed the limits shown in Table 17. Any heat sink design should avoid loads on corners and edges of die. The CPGA package has compliant pads that serve to bring surfaces in planar contact. Tool-assisted zero insertion force sockets should be designed so that no load is placed on the ceramic substrate of the package. Table 17 shows the mechanical loading specifications for the processor die. Table 17. Mechanical Loading Location Dynamic (MAX) Static (MAX) Units Note Die Surface 100 30 lbf 1 Die Edge 10 10 lbf 2 Notes: 1. Load specified for coplanar contact to die surface. 2. Load defined for a surface at no more than a two degree angle of inclination to die surface. Chapter 9 Mechanical Data 47 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 9.3 24310G--January 2002 CPGA Package Description Figure 13 on page 49 shows a diagram and notes for the AMD Duron processor model 7 CPGA package. Table 18 provides the dimensions in millimeters assigned to the letters and symbols shown in the Figure 13 diagram. Table 18. Dimensions for the AMD DuronTM Processor Model 7 CPGA Package Letter or Symbol D/E Maximum Minimum 1 Dimension Dimension1 49.27 49.78 Letter or Symbol Maximum Minimum 1 Dimension Dimension1 E9 1.66 1.96 -- 4.50 D1/E1 45.72 BSC G/H D2 11.698 REF A 2.24 REF D3 3.30 3.60 A1 1.27 1.53 D4 11.84 12.39 A2 0.80 0.88 D5 11.84 12.39 A3 0.116 -- D6 5.91 6.46 A4 -- 1.90 D7 10.65 11.20 P -- 6.60 D8 3.05 3.35 b 0.43 0.50 E2 b1 9.034 REF 1.40 REF E3 2.35 2.65 S 1.435 2.375 E4 7.25 7.80 L 3.05 3.31 E5 7.25 7.80 M 37 E6 8.86 9.41 N 453 (pins) E7 8.86 9.41 e 1.27 BSC E8 15.59 16.38 e1 2.54 BSC Note: 1. Dimensions are given in millimeters. 48 Mechanical Data Chapter 9 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Figure 13. AMD DuronTM Processor Model 7 CPGA Package Chapter 9 Mechanical Data 49 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 50 24310G--January 2002 Mechanical Data Chapter 9 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 10 10.1 Pin Descriptions Pin Diagram and Pin Name Abbreviations Figure 14 on page 52 shows the staggered Ceramic Pin Grid Array (CPGA) for the AMD DuronTM processor model 7. Because some of the pin names are too long to fit in the grid, they are abbreviated. Figure 15 on page 53 show s the bottomside view of the array. Table 19 on page 54 lists all the pins in alphabetical order by pin name, along with the abbreviation where necessary. Chapter 10 Pin Descriptions 51 52 Pin Descriptions Z X V T R P AN AM AL 1 INTR IGNNE# FERR A20M# STPC# DBRDY FID[2] FID[0] TDI SCNCK1 TCK PICCLK VID[0] SAO#0 SAO#10 SAO#11 SAO#7 1 2 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS 2 3 3 NMI FLUSH# INIT# RESET# PWROK PLTST# DBREQ# FID[3] FID[1] TRST# SCNINV TMS PICD#0 VID[1] SAO#1 SAO#14 SAOC# SAO#9 SAO#12 4 VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC 4 5 5 SMI# VCC VCC NC ZP ZN NC NC VREF_S TDO SCNCK2 SCNSN PICD#1 VID[2] NC SAO#13 SAO#4 SAO#8 SAO#5 6 VSS CPR# AMD NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS 6 7 7 NC NC NC KEY NC NC KEY KEY NC THDC THDA KEY KEY VID[3] VID[4] KEY SAO#6 SAO#2 SAO#3 8 NC NC NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC 8 9 10 VCC VCC VCC NC NC VSS VSS VSS 10 11 11 NC NC NC COREFB NC SD#50 SDOC#3 SD#61 12 VSS VSS VSS VSS VCC VCC VCC VCC 12 13 13 PLMN1 PLMN2 ANLOG COREFB# NC SD#49 NC SD#53 14 VCC VCC VCC VCC VSS VSS VSS VSS 14 15 VCC VCC VCC VCC 16 17 KEY SD#48 SD#60 SD#62 VSS VSS VSS VSS 18 NC SD#58 SD#59 NC 19 VCC VCC VCC VCC 20 21 NC SD#36 SD#56 SD#57 VSS VSS VSS VSS 22 23 KEY SD#46 SD#37 SD#39 15 PLBYC PLBYC# NC KEY 16 VSS VSS VSS VSS 17 CLKIN CLKIN# NC KEY 18 VCC VCC VCC VCC 19 RCLK RCLK# NC NC 20 VSS VSS VSS VSS 21 K7CO# K7CO CLKFR NC 22 VCC VCC VCC VCC 23 PRCRDY CNNCT VCCA NC AMD DuronTM Processor Model 7 Topside View KEY SDIC#3 SD#51 SD#63 24 VSS VSS VSS VSS VCC VCC VCC VCC 24 25 25 NC NC PLBYP# NC KEY NC SD#47 SD#35 26 VCC VCC VCC VCC VSS VSS VSS VSS 26 27 27 NC NC NC KEY NC SDIC#2 SD#38 SD#34 28 VSS VSS VSS NC NC VCC VCC VCC 28 29 29 SAI#12 SAI#1 SAI#0 KEY NC SD#33 SD#45 SD#44 Figure 14. AMD DuronTM Processor Model 7 Pin Diagram--Topside View 9 NC NC NC KEY KEY SD#52 SD#54 SD#55 30 VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS 30 31 SAI#14 SDOV# SFILLV# NC NC NC NC NC NC NC NC NC NC NC NC NC SD#32 SD#43 NC 31 32 VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VCC VCC VCC 32 33 33 SDINV# SAI#8 SAIC# SAI#2 SAI#5 SD#10 SD#8 NC SDIC#0 SD#5 SD#7 SD#24 SD#25 SD#26 SD#19 SD#20 NC SD#42 SDOC#2 34 VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS 34 35 35 SAI#13 SAI#4 SAI#6 SAI#11 SDOC#0 SD#14 SD#0 SD#3 SD#2 SD#4 SD#15 SD#17 SD#27 NC SDIC#1 SD#23 SD#31 SD#41 SD#40 36 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC 36 37 37 SAI#9 SAI#10 SAI#3 SAI#7 SD#9 SD#11 SD#13 SD#12 SD#1 NC SD#6 SD#16 SD#18 SD#28 SD#29 SD#21 SD#22 SDOC#1 SD#30 Z X V T R P AN AM AL AK AJ AH AG AF AE AD AC AB AA Y K H F D B M W U S Q N L J G E C A AMD DuronTM Processor Model 7 Data Sheet AK AJ AH AG AF AE AD AC AB AA Y K H F D B M W U S Q N L J G E C A Preliminary Information 24310G--January 2002 Chapter 10 Chapter 10 8 6 4 2 10 Pin Descriptions 37 36 35 C C A SD#41 SD#42 SD#43 SD#45 SD#38 SD#47 SD#37 SD#56 SD#59 SD#60 SD#51 NC SDOC#3 SD#54 SAO#2 SAO#8 SAO#9 SAO#7 SDOC#1 B VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS B SD#30 SD#40 SDOC#2 NC SD#44 SD#34 SD#35 SD#39 SD#57 NC SD#62 SD#63 SD#53 SD#61 SD#55 SAO#3 SAO#5 SAO#12 A D VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC D E E SD#22 SD#31 NC SD#32 SD#33 SDIC#2 NC SD#46 SD#36 SD#58 SD#48 SDIC#3 SD#49 SD#50 SD#52 SAO#6 SAO#4 SAOC# SAO#11 F VCC VCC VCC NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS F G G SD#21 SD#23 SD#20 NC NC NC KEY KEY NC NC KEY KEY NC NC KEY KEY SAO#13 SAO#14 SAO#10 J J SD#29 SDIC#1 SD#19 NC VID[4] NC SAO#1 SAO#0 K VCC VCC VCC NC NC VSS VSS VSS K L L SD#28 NC SD#26 NC VID[3] VID[2] VID[1] VID[0] M VSS VSS VSS VSS VCC VCC VCC VCC M N N SD#18 SD#27 SD#25 NC KEY PICD#1 PICD#0 PICCLK P VCC VCC VCC VCC VSS VSS VSS VSS P Q VCC VCC VCC VCC R S THDA SCNCK2 SCNINV SCNCK1 VSS VSS VSS VSS T U THDC TDO TRST# TDI VCC VCC VCC VCC V W NC VREF_S FID[1] FID[0] VSS VSS VSS VSS X Y KEY NC FID[3] FID[2] Q SD#16 SD#17 SD#24 NC R VSS VSS VSS VSS S SD#6 SD#15 SD#7 NC T VCC VCC VCC VCC U NC SD#4 SD#5 NC V VSS VSS VSS VSS W SD#1 SD#2 SDIC#0 NC X VCC VCC VCC VCC Y SD#12 SD#3 NC NC AMD DuronTM Processor Model 7 Bottomside View KEY SCNSN TMS TCK Z VSS VSS VSS VSS VCC VCC VCC VCC Z AA AA SD#13 SD#0 SD#8 NC KEY NC DBREQ# DBRDY AB VCC VCC VCC VCC VSS VSS VSS VSS AB AC AC SD#11 SD#14 SD#10 NC NC ZN PLTST# STPC# AD VSS VSS VSS NC NC VCC VCC VCC AD AE AE SD#9 SDOC#0 SAI#5 NC NC ZP PWROK A20M# AF VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS AF Figure 15. AMD DuronTM Processor Model 7 Pin Diagram--Bottomside View H VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC H AG AG SAI#7 SAI#11 SAI#2 NC KEY KEY NC NC NC NC KEY KEY COREFB# COREFB KEY KEY NC RESET# FERR AH VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC AMD VCC VCC AH AJ AJ SAI#3 SAI#6 SAIC# SFILLV# SAI#0 NC PLBYP# VCCA CLKFR NC NC NC ANLOG NC NC NC VCC INIT# IGNNE# AK VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC CPR# VSS VSS AK AL AL SAI#10 SAI#4 SAI#8 SDOV# SAI#1 NC NC CNNCT K7CO RCLK# CLKIN# PLBYC# PLMN2 NC NC NC VCC FLUSH# INTR AM VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VSS VSS VCC AM AN SAI#9 SAI#13 SDINV# SAI#14 SAI#12 NC NC PRCRDY K7CO# RCLK CLKIN PLBYC PLMN1 NC NC NC SMI# NMI AN 8 6 4 2 10 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 5 3 1 AMD DuronTM Processor Model 7 Data Sheet 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 5 3 1 Preliminary Information 24310G--January 2002 53 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations Abbreviation ANLOG CLKFR CNNCT CPR# K7CO K7CO# 54 Full Name A20M# AMD ANALOG CLKFWDRST CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY Table 19. Pin Name Abbreviations (continued) Pin AE1 AH6 AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AK6 AA1 AA3 AG1 W1 W3 Y1 Y3 AL3 AJ1 AJ3 AL1 AL21 AN21 G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 AG29 Abbreviation Pin Descriptions Full Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin A19 A31 C13 E25 E33 F8 F30 G11 G13 G19 G21 G27 G29 G31 H6 H8 H10 H28 H30 H32 J5 J31 K8 K30 L31 L35 N31 Q31 S31 U31 U37 W7 W31 Y5 Y31 Y33 AA5 AA31 AC7 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations (continued) Abbreviation Full Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NMI Chapter 10 Pin AC31 AD8 AD30 AE7 AE31 AF6 AF8 AF10 AF28 AF30 AF32 AG5 AG19 AG21 AG23 AG25 AG31 AH8 AH30 AJ7 AJ9 AJ11 AJ15 AJ17 AJ19 AJ27 AK8 AL7 AL9 AL11 AL25 AL27 AM8 AN7 AN9 AN11 AN25 AN27 AN3 Table 19. Pin Name Abbreviations (continued) Abbreviation PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST# PRCRDY RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 Pin Descriptions Full Name PICCLK PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# Pin N1 N3 N5 AJ25 AN15 AL15 AN13 AL13 AC3 AN23 AE3 AG3 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33 J1 J3 C7 A7 E5 A5 E7 C1 C5 55 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations (continued) Table 19. Pin Name Abbreviations (continued) Abbreviation SAO#9 SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1 SCNCK2 SCNINV SCNSN SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 Abbreviation SD#28 SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 56 Full Name SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 SCANCLK2 SCANINTEVAL SCANSHIFTEN SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# Pin C3 G1 E1 A3 G5 G3 E3 S1 S5 S3 Q5 AA35 W37 W35 Y35 U35 U33 S37 S33 AA33 AE37 AC33 AC37 Y37 AA37 AC35 S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 Pin Descriptions Full Name SDATA[28]# SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# Pin L37 J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15 E9 A13 C9 A9 C21 A21 E19 C19 C17 A11 A17 A15 W33 J35 E27 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations (continued) Abbreviation SDIC#3 SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# THDA THDC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Chapter 10 Full Name SDATAINCLK[3]# SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# TCK TDI TDO THERMDA THERMDC TMS TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin E15 AN33 AE35 C37 A33 C11 AL31 AJ31 AN5 AC1 Q1 U1 U5 S7 U7 Q3 U3 B4 B8 B12 B16 B20 B24 B28 B32 B36 D2 D4 D8 D12 D16 D20 D24 D28 D32 F12 F16 F20 F24 Table 19. Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Descriptions Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin F28 F32 F34 F36 H2 H4 H12 H16 H20 H24 K32 K34 K36 M2 M4 M6 M8 P30 P32 P34 P36 R2 R4 R6 R8 T30 T32 T34 T36 V2 V4 V6 V8 X30 X32 X34 X36 Z2 Z4 57 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 58 Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin Z6 Z8 AB30 AB32 AB34 AB36 AD2 AD4 AD6 AF14 AF18 AF22 AF26 AF34 AF36 AH2 AH4 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AJ5 AL5 AM2 AM10 AM14 AM18 AM22 AM26 AM22 Table 19. Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VREF_S Pin Descriptions Full Name VCC_CORE VCC_CORE VCC_CORE VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AM26 AM30 AM34 AJ23 L1 L3 L5 L7 J7 W5 B2 B6 B10 B14 B18 B22 B26 B30 B34 D6 D10 D14 D18 D22 D26 D30 D34 D36 F2 F4 F6 F10 F14 F18 F22 F26 H14 H18 H22 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 19. Pin Name Abbreviations (continued) Abbreviation Full Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Chapter 10 Pin H26 H34 H36 K2 K4 K6 M30 M32 M34 M36 P2 P4 P6 P8 R30 R32 R34 R36 T2 T4 T6 T8 V30 V32 V34 V36 X2 X4 X6 X8 Z30 Z32 Z34 Z36 AB2 AB8 AB4 AB6 AD32 Table 19. Pin Name Abbreviations (continued) Abbreviation Pin Descriptions Full Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ZN ZP Pin AD34 AD36 AF2 AF4 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK2 AK4 AK12 AK16 AK20 AK24 AK28 AK32 AM4 AM6 AM12 AM16 AM20 AM24 AM28 AM32 AM36 AC5 AE5 59 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 10.2 24310G--January 2002 Pin List Table 20 cross-references Socket A pin location to signal name. The "L" (Level) column shows the electrical specification for this pin. "P" indicates a push-pull mode driven by a single source. "O" indicates open-drain mode that allows devices to share the pin. Note: The AMD Duron processor supports push-pull drivers. For more information, see "Push-Pull (PP) Drivers" on page 6. The "P" (Port) column indicates if this signal is an input (I), output (O), or bidirectional (B) signal. The "R" (Reference) column indicates if this signal should be referenced to VSS (G) or VCC_CORE (P) planes for the purpose of signal routing with respect to the current return paths. Table 20. Cross-Reference by Pin Location Pin Name Table 20. Cross-Reference by Pin Location Description L P R page 72 - - - B2 Pin Name Description L P R VSS - - - A1 No Pin A3 SADDOUT[12]# P O G B4 VCC_CORE - - - A5 SADDOUT[5]# P O G B6 VSS - - - A7 SADDOUT[3]# P O G B8 VCC_CORE - - - A9 SDATA[55]# P B P B10 VSS - - - A11 SDATA[61]# P B P B12 VCC_CORE - - - A13 SDATA[53]# P B G B14 VSS - - - A15 SDATA[63]# P B G B16 VCC_CORE - - - A17 SDATA[62]# P B G B18 VSS - - - A19 NC Pin - - - B20 VCC_CORE - - - A21 SDATA[57]# P B G B22 VSS - - - A23 SDATA[39]# P B G B24 VCC_CORE - - - A25 SDATA[35]# P B P B26 VSS - - - A27 SDATA[34]# P B P B28 VCC_CORE - - - A29 SDATA[44]# P B G B30 VSS - - - A31 NC Pin - - - B32 VCC_CORE - - - A33 SDATAOUTCLK[2]# P O P B34 VSS - - - A35 SDATA[40]# P B G B36 VCC_CORE - - - A37 SDATA[30]# P B P C1 SADDOUT[7]# P O G 60 page 72 page 72 Pin Descriptions Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R C3 SADDOUT[9]# P O G D34 VSS - - - C5 SADDOUT[8]# P O G D36 VSS - - - C7 SADDOUT[2]# P O G E1 SADDOUT[11]# P O P C9 SDATA[54]# P B P E3 SADDOUTCLK# P O G C11 SDATAOUTCLK[3]# P O G E5 SADDOUT[4]# P O P C13 NC Pin - - - E7 SADDOUT[6]# P O G C15 SDATA[51]# P B P E9 SDATA[52]# P B P C17 SDATA[60]# P B G E11 SDATA[50]# P B P C19 SDATA[59]# P B G E13 SDATA[49]# P B G C21 SDATA[56]# P B G E15 SDATAINCLK[3]# P I G C23 SDATA[37]# P B P E17 SDATA[48]# P B P C25 SDATA[47]# P B G E19 SDATA[58]# P B G C27 SDATA[38]# P B G E21 SDATA[36]# P B P C29 SDATA[45]# P B G E23 SDATA[46]# P B P C31 SDATA[43]# P B G E25 NC Pin - - - C33 SDATA[42]# P B G E27 SDATAINCLK[2]# P I G C35 SDATA[41]# P B G E29 SDATA[33]# P B P C37 SDATAOUTCLK[1]# P O G E31 SDATA[32]# P B P D2 VCC_CORE - - - E33 NC Pin - - - D4 VCC_CORE - - - E35 SDATA[31]# P B P D6 VSS - - - E37 SDATA[22]# P B G D8 VCC_CORE - - - F2 VSS - - - D10 VSS - - - F4 VSS - - - D12 VCC_CORE - - - F6 VSS - - - D14 VSS - - - F8 NC Pin - - - D16 VCC_CORE - - - F10 VSS - - - D18 VSS - - - F12 VCC_CORE - - - D20 VCC_CORE - - - F14 VSS - - - D22 VSS - - - F16 VCC_CORE - - - D24 VCC_CORE - - - F18 VSS - - - D26 VSS - - - F20 VCC_CORE - - - D28 VCC_CORE - - - F22 VSS - - - D30 VSS - - - F24 VCC_CORE - - - D32 VCC_CORE - - - F26 VSS - - - Chapter 10 page 72 Pin Descriptions page 72 page 72 page 72 61 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin - - - H22 - - - Name Description L P R VSS - - - H24 VCC_CORE - - - - - - F28 VCC_CORE F30 NC Pin F32 VCC_CORE - - - H26 VSS F34 VCC_CORE - - - H28 NC Pin page 72 - - - F36 VCC_CORE - - - H30 NC Pin page 72 - - - G1 SADDOUT[10]# P O P H32 NC Pin page 72 - - - G3 SADDOUT[14]# P O G H34 VSS - - - G5 SADDOUT[13]# P O G H36 VSS - - - G7 Key Pin page 71 - - - J1 SADDOUT[0]# page 72 P O - G9 Key Pin page 71 - - - J3 SADDOUT[1]# page 72 P O - G11 NC Pin page 72 - - - J5 NC Pin page 72 - - - G13 NC Pin page 72 - - - J7 VID[4] page 73 O O - G15 Key Pin page 71 - - - J31 NC Pin page 72 - - - G17 Key Pin page 71 - - - J33 SDATA[19]# P B G G19 NC Pin page 72 - - - J35 SDATAINCLK[1]# P I P G21 NC Pin page 72 - - - J37 SDATA[29]# P B P G23 Key Pin page 71 - - - K2 VSS - - - G25 Key Pin page 71 - - - K4 VSS - - - G27 NC Pin page 72 - - - K6 VSS - - - G29 NC Pin page 72 - - - K8 NC Pin page 72 - - - G31 NC Pin page 72 - - - K30 NC Pin page 72 - - - G33 SDATA[20]# P B G K32 VCC_CORE - - - G35 SDATA[23]# P B G K34 VCC_CORE - - - G37 SDATA[21]# P B G K36 VCC_CORE - - - H2 VCC_CORE - - - L1 VID[0] page 73 O O - H4 VCC_CORE - - - L3 VID[1] page 73 O O - H6 NC Pin page 72 - - - L5 VID[2] page 73 O O - H8 NC Pin page 72 - - - L7 VID[3] page 73 O O - H10 NC Pin page 72 - - - L31 NC Pin page 72 - - - H12 VCC_CORE - - - L33 SDATA[26]# P B P H14 VSS - - - L35 NC Pin - - - H16 VCC_CORE - - - L37 SDATA[28]# P B P H18 VSS - - - M2 VCC_CORE - - - H20 VCC_CORE - - - M4 VCC_CORE - - - 62 page 72 Pin Descriptions page 72 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R M6 VCC_CORE - - - R30 VSS - - - M8 VCC_CORE - - - R32 VSS - - - M30 VSS - - - R34 VSS - - - M32 VSS - - - R36 VSS - - - M34 VSS - - - S1 SCANCLK1 page 72 P I - M36 VSS - - - S3 SCANINTEVAL page 72 P I - N1 PICCLK page 68 O I - S5 SCANCLK2 page 72 P I - N3 PICD#[0] page 68 O B - S7 THERMDA page 73 - - - N5 PICD#[1] page 68 O B - S31 NC Pin page 72 - - - N7 Key Pin page 71 - - - S33 SDATA[7]# P B G N31 NC Pin page 72 - - - S35 SDATA[15]# P B P N33 SDATA[25]# P B P S37 SDATA[6]# P B G N35 SDATA[27]# P B P T2 VSS - - - N37 SDATA[18]# P B G T4 VSS - - - P2 VSS - - - T6 VSS - - - P4 VSS - - - T8 VSS - - - P6 VSS - - - T30 VCC_CORE - - - P8 VSS - - - T32 VCC_CORE - - - P30 VCC_CORE - - - T34 VCC_CORE - - - P32 VCC_CORE - - - T36 VCC_CORE - - - P34 VCC_CORE - - - U1 TDI page 71 P I - P36 VCC_CORE - - - U3 TRST# page 71 P I - Q1 TCK page 71 P I - U5 TDO page 71 P O - Q3 TMS page 71 P I - U7 THERMDC page 73 - - - Q5 SCANSHIFTEN page 72 P I - U31 NC Pin page 72 - - - Q7 Key Pin page 71 - - - U33 SDATA[5]# P B G Q31 NC Pin page 72 - - - U35 SDATA[4]# P B G Q33 SDATA[24]# P B P U37 NC Pin - - - Q35 SDATA[17]# P B G V2 VCC_CORE - - - Q37 SDATA[16]# P B G V4 VCC_CORE - - - R2 VCC_CORE - - - V6 VCC_CORE - - - R4 VCC_CORE - - - V8 VCC_CORE - - - R6 VCC_CORE - - - V30 VSS - - - R8 VCC_CORE - - - V32 VSS - - - Chapter 10 Pin Descriptions page 72 63 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R V34 VSS - - - AA1 DBRDY page 69 P O - V36 VSS - - - AA3 DBREQ# page 69 P I - W1 FID[0] page 70 O O - AA5 NC - - - W3 FID[1] page 70 O O - AA7 Key Pin page 71 - - - W5 VREFSYS page 74 P - - AA31 NC Pin page 72 - - - W7 NC Pin page 72 - - - AA33 SDATA[8]# P B P W31 NC Pin page 72 - - - AA35 SDATA[0]# P B G W33 SDATAINCLK[0]# P I G AA37 SDATA[13]# P B G W35 SDATA[2]# P B G AB2 VSS - - - W37 SDATA[1]# P B P AB4 VSS - - - X2 VSS - - - AB6 VSS - - - X4 VSS - - - AB8 VSS - - - X6 VSS - - - AB30 VCC_CORE - - - X8 VSS - - - AB32 VCC_CORE - - - X30 VCC_CORE - - - AB34 VCC_CORE - - - X32 VCC_CORE - - - AB36 VCC_CORE - - - X34 VCC_CORE - - - AC1 STPCLK# page 73 P I - X36 VCC_CORE - - - AC3 PLLTEST# page 72 P I - Y1 FID[2] page 70 O O - AC5 ZN page 74 P - - Y3 FID[3] page 70 O O - AC7 NC - - - Y5 NC Pin page 72 - - - AC31 NC Pin - - - Y7 Key Pin page 71 - - - AC33 SDATA[10]# P B P Y31 NC Pin page 72 - - - AC35 SDATA[14]# P B G Y33 NC Pin page 72 - - - AC37 SDATA[11]# P B G Y35 SDATA[3]# P B G AD2 VCC_CORE - - - Y37 SDATA[12]# P B P AD4 VCC_CORE - - - Z2 VCC_CORE - - - AD6 VCC_CORE - - - Z4 VCC_CORE - - - AD8 NC Pin page 72 - - - Z6 VCC_CORE - - - AD30 NC Pin page 72 - - - Z8 VCC_CORE - - - AD32 VSS - - - Z30 VSS - - - AD34 VSS - - - Z32 VSS - - - AD36 VSS - - - Z34 VSS - - - AE1 A20M# P I - Z36 VSS - - - AE3 PWROK P I - 64 Pin Descriptions page 72 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin page 74 P - - AG21 - - - - - Name Description L P R NC Pin page 72 - - - AG23 NC Pin page 72 - - - - AG25 NC Pin page 72 - - - AE5 ZP AE7 NC AE31 NC Pin AE33 SADDIN[5]# P I G AG27 Key Pin page 71 - - - AE35 SDATAOUTCLK[0]# P O P AG29 Key Pin page 71 - - - AE37 SDATA[9]# P B G AG31 NC Pin page 72 - - - AF2 VSS - - - AG33 SADDIN[2]# P I G AF4 VSS - - - AG35 SADDIN[11]# P I G AF6 NC Pin page 72 - - - AG37 SADDIN[7]# P I P AF8 NC Pin page 72 - - - AH2 VCC_CORE - - - AF10 NC Pin page 72 - - - AH4 VCC_CORE - - - AF12 VSS - - - AH6 AMD Pin page 68 - - - AF14 VCC_CORE - - - AH8 NC Pin page 72 - - - AF16 VSS - - - AH10 VCC_CORE - - - AF18 VCC_CORE - - - AH12 VSS - - - AF20 VSS - - - AH14 VCC_CORE - - - AF22 VCC_CORE - - - AH16 VSS - - - AF24 VSS - - - AH18 VCC_CORE - - - AF26 VCC_CORE - - - AH20 VSS - - - AF28 NC Pin page 72 - - - AH22 VCC_CORE - - - AF30 NC Pin page 72 - - - AH24 VSS - - - AF32 NC Pin page 72 - - - AH26 VCC_CORE - - - AF34 VCC_CORE - - - AH28 VSS - - - AF36 VCC_CORE - - - AH30 NC Pin - - - AG1 FERR P O - AH32 VSS - - - AG3 RESET# - I - AH34 VSS - - - AG5 NC Pin page 72 - - - AH36 VSS - - - AG7 Key Pin page 71 - - - AJ1 IGNNE# page 71 P I - AG9 Key Pin page 71 - - - AJ3 INIT# page 71 P I - AG11 COREFB page 69 - - - AJ5 VCC_CORE - - - AG13 COREFB# page 69 - - - AJ7 NC Pin page 72 - - - AG15 Key Pin page 71 - - - AJ9 NC Pin page 72 - - - AG17 Key Pin page 71 - - - AJ11 NC Pin page 72 - - - AG19 NC Pin page 72 - - - AJ13 Analog page 68 - - - Chapter 10 page 72 page 69 Pin Descriptions page 72 65 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued)Table 20. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R AJ15 NC Pin page 72 - - - AL9 NC Pin page 72 - - - AJ17 NC Pin page 72 - - - AL11 NC Pin page 72 - - - AJ19 NC Pin page 72 - - - AL13 PLLMON2 page 72 O O - AJ21 CLKFWDRST page 68 P I P AL15 PLLBYPASSCLK# page 72 P I - AJ23 VCCA page 73 - - - AL17 CLKIN# page 68 P I P AJ25 PLLBYPASS# page 72 P I - AL19 RSTCLK# page 68 P I P AJ27 NC Pin page 72 - - - AL21 K7CLKOUT page 71 P O - AJ29 SADDIN[0]# page 72 P I - AL23 CONNECT page 69 P I P AJ31 SFILLVALID# P I G AL25 NC Pin page 72 - - - AJ33 SADDINCLK# P I G AL27 NC Pin page 72 - - - AJ35 SADDIN[6]# P I P AL29 SADDIN[1]# page 72 P I - AJ37 SADDIN[3]# P I G AL31 SDATAOUTVALID# P O P AK2 VSS - - - AL33 SADDIN[8]# P I P AK4 VSS - - - AL35 SADDIN[4]# P I G AK6 CPU_PRESENCE# page 69 - - - AL37 SADDIN[10]# P I G AK8 NC Pin page 72 - - - AM2 VCC_CORE - - - AK10 VCC_CORE - - - AM4 VSS - - - AK12 VSS - - - AM6 VSS - - - AK14 VCC_CORE - - - AM8 NC Pin - - - AK16 VSS - - - AM10 VCC_CORE - - - AK18 VCC_CORE - - - AM12 VSS - - - AK20 VSS - - - AM14 VCC_CORE - - - AK22 VCC_CORE - - - AM16 VSS - - - AK24 VSS - - - AM18 VCC_CORE - - - AK26 VCC_CORE - - - AM20 VSS - - - AK28 VSS - - - AM22 VCC_CORE - - - AK30 VCC_CORE - - - AM24 VSS - - - AK32 VSS - - - AM26 VCC_CORE - - - AK34 VCC_CORE - - - AM28 VSS - - - AK36 VCC_CORE - - - AM30 VCC_CORE - - - AL1 INTR page 71 P I - AM32 VSS - - - AL3 FLUSH# page 71 P I - AM34 VCC_CORE - - - AL5 VCC_CORE - - - AM36 VSS - - - AL7 NC Pin - - - AN1 No Pin - - - 66 page 72 Pin Descriptions page 72 page 72 Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 20. Cross-Reference by Pin Location (continued) Pin Name Description L P R AN3 NMI P I - AN5 SMI# P I - AN7 NC Pin page 72 - - - AN9 NC Pin page 72 - - - AN11 NC Pin page 72 - - - AN13 PLLMON1 page 72 O B - AN15 PLLBYPASSCLK page 72 P I - AN17 CLKIN page 68 P I P AN19 RSTCLK page 68 P I P AN21 K7CLKOUT# page 71 P O - AN23 PROCRDY P O P AN25 NC Pin page 72 - - - AN27 NC Pin page 72 - - - AN29 SADDIN[12]# P I G AN31 SADDIN[14]# P I G AN33 SDATAINVALID# P I P AN35 SADDIN[13]# P I G AN37 SADDIN[9]# P I G Chapter 10 Pin Descriptions 67 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 10.3 24310G--January 2002 Detailed Pin Descriptions The information in this section pertains to Table 20 on page 60. A20M# Pin A20M# is an input from the system used to simulate address wrap-around in the 20-bit 8086. AMD Pin AMD Socket A processors do not implement a pin at location AH6. All Socket A designs must have a top plate or cover that blocks this pin location. When the cover plate blocks this location, a non-AMD part (e.g., PGA370) does not fit into the socket. However, socket manufacturers are allowed to have a contact loaded in the AH6 position. Therefore, motherboard socket design should account for the possibility that a contact could be loaded in this position. AMD DuronTM System Bus Pins See the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for information about the system bus pins -- PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Analog Pin Treat this pin as a NC. APIC Pins, PICCLK, PICD[1:0]# The Advanced Programmable Interrupt Controller (APIC) is a feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor. The pins, PICD[1:0], are the bi-directional message-passing signals used for the APIC and are driven to the Southbridge or a dedicated I/O APIC. The pin, PICCLK, must be driven with a valid clock input. For more information, see Table 16, "APIC Pin AC and DC Characteristics," on page 41. CLKFWDRST Pin CLKFWDRST resets clock-forward circuitry for both the system and processor. CLKIN, RSTCLK (SYSCLK) Pins Connect CLKIN with RSTCLK and name it SYSCLK. Connect CLKIN# with RSTCLK# and name it SYSCLK#. Length match the clocks from the clock generator to the Northbridge and processor. 68 Pin Descriptions Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 See "SYSCLK and SYSCLK#" on page 73 for more information. CONNECT Pin CONNECT is an input from the system used for power management and clock-forward initialization at reset. COREFB and COREFB# Pins COREFB and COREFB# are outputs to the system that provide processor core voltage feedback to the system. CPU_PRESENCE# Pin CPU_PRESENCE# is connected to VSS on the processor package. If pulled-up on the motherboard, CPU_PRESENCE# may be used to detect the presence or absence of a processor in the Socket A-style socket. DBRDY and DBREQ# Pins DBRDY and DBREQ# are routed to the debug connector. DBREQ# is tied to VCC_CORE with a pullup resistor. FERR Pin FERR is an output to the system that is asserted for any unmasked numerical exception independent of the NE bit in CR0. FERR is a push-pull active High signal that must be inverted and level shifted to an active Low signal. For more information about FERR and FERR#, see the "Required Circuits" chapter of the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. Chapter 10 Pin Descriptions 69 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet FID[3:0] Pins 24310G--January 2002 FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the 4-bit processor clock-to-SYSCLK ratio. Table 21 describes the encodings of the clock multipliers on FID[3:0]. Table 21. FID[3:0] Clock Multiplier Encodings FID[3] FID[2] FID[1] FID[0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Processor Clock to SYSCLK Frequency Ratio 11 11.5 12 12.5* 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 Note: *All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes the SIP configuration for all ratios of 12.5x or greater to be the same. The FID[3:0] signals are open drain processor outputs that are pulled High on the motherboard and sampled by the chipset to determine the SIP (Serialization Initialization Packet) that is sent to the processor. The FID[3:0] signals are valid after PWROK is asserted. The FID[3:0]signals must not be sampled u n t i l t h ey b e c o m e va l i d . S e e t h e A M D A t h l o n TM a n d AMD DuronTM System Bus Specification, order# 21902 for more information about Serialization Initialization Packets and SIP protocol. The processor FID[3:0] outputs are open drain and 2.5 V tolerant. To prevent damage to the processor, if these signals are pulled High to above 2.5 V, they must be electrically 70 Pin Descriptions Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 isolated from the processor. For information about the FID[3:0] isolation circuit, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. See "Frequency Identification (FID[3:0])" on page 27 for the DC characteristics for FID[3:0]. FLUSH# Pin FLUSH# must be tied to VCC_CORE with a pullup resistor. If a debug connector is implemented, FLUSH# is routed to the debug connector. IGNNE# Pin IGNNE# is an input from the system that tells the processor to ignore numeric errors. INIT# Pin INIT# is an input from the system that resets the integer registers without affecting the floating-point registers or the internal caches. Execution starts at 0_FFFF_FFF0h. INTR Pin INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. JTAG Pins TCK, TMS, TDI, TRST#, and TDO are the JTAG interface. Connect these pins directly to the motherboard debug connector. Pull TDI, TCK, TMS, and TRST# up to VCC_CORE with pullup resistors. K7CLKOUT and K7CLKOUT# Pins K7CLKOUT and K7CLKOUT# are each run for two to three inches and then terminated with a resistor pair: 100 ohms to VCC_CORE and 100 ohms to VSS. The effective termination resistance and voltage are 50 ohms and VCC_CORE/2. Key Pins These 16 locations are for processor type keying for forwards and backwards compatibility (G7, G9, G15, G17, G23, G25, N7, Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29). Motherboard designers should treat key pins like NC (No Connect) pins. A socket designer has the option of creating a top mold piece that allows PGA key pins only where designated. However, sockets that populate all 16 key pins must be allowed, so the motherboard must always provide for pins at all key pin locations. See "NC Pins" for more information. Chapter 10 Pin Descriptions 71 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 NC Pins The motherboard should provide a plated hole for an NC pin. The pin hole should not be electrically connected to anything. NMI Pin NMI is an input from the system that causes a non-maskable interrupt. PGA Orientation Pins No pin is present at pin locations A1 and AN1. Motherboard designers should not allow for a PGA socket pin at these locations. For more information, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. PLL Bypass and Test Pins P L LT E S T # , P L L B Y PA S S # , P L L M O N 1 , P L L M O N 2 , PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass and test interface. This interface is tied disabled on the motherboard. All six pin signals are routed to the debug connector. All four processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup resistors. PWROK Pin The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. For more information, Chapter 8, "Signal and Power-Up Requirements" on page 43. SADDIN[1:0]# and SADDOUT[1:0]# Pins The A M D D u ro n p ro c e s s o r m o d e l 7 d oe s n o t s u p p o r t SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC with pullup resistors, if this bit is not supported by the Northbridge (future models can support SADDIN[1]#). SADDOUT[1:0]# are tied to VCC with pullup resistors if these pins are supported by the Northbridge. For more information, see the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. Scan Pins SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2 are the scan interface. This interface is AMD internal and is tied disabled with pulldown resistors to ground on the motherboard. SMI# Pin SMI# is an input that causes the processor to enter the system management mode. 72 Pin Descriptions Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 STPCLK# Pin STPCLK# is an input that causes the processor to enter a lower power mode and issue a Stop Grant special cycle. SYSCLK and SYSCLK# SYSCLK and SYSCLK# are differential input clock signals provided to the PLL of the processor from a system-clock generator. See "CLKIN, RSTCLK (SYSCLK) Pins" on page 68 for more information. THERMDA and THERMDC Pins Thermal Diode anode and cathode pins are used to monitor the actual temperature of the processor die, providing more accurate temperature control to the system. See Table 14, "Thermal Diode Electrical Characteristics," on page 39 for more information. VCCA Pin VCCA is the processor PLL supply. For information about the VCCA pin, see Table 5, "VCCA AC and DC Characteristics," on page 35 and the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. VID[4:0] Pins The VID[4:0] (Voltage Identification) outputs are used to dictate the VCC_CORE voltage level. The VID[4:0] pins are strapped to ground or left unconnected on the processor package. The VID[4:0] pins are pulled-up on the motherboard and used by the VCC_CORE DC/DC converter. For more information, see Table 22, "VID[4:0] Code to Voltage Definition," on page 74. Chapter 10 Pin Descriptions 73 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 22. VID[4:0] Code to Voltage Definition VID[4:0] VCC_CORE (V) VID[4:0] VCC_CORE (V) 00000 1.850 10000 1.450 00001 1.825 10001 1.425 00010 1.800 10010 1.400 00011 1.775 10011 1.375 00100 1.750 10100 1.350 00101 1.725 10101 1.325 00111 1.675 10111 1.275 01000 1.650 11000 1.250 01001 1.625 11001 1.225 01010 1.600 11010 1.200 01011 1.575 11011 1.175 01100 1.550 11100 1.150 01101 1.525 11101 1.125 01110 1.500 11110 1.100 01111 1.475 11111 No CPU For more information, see the "Required Circuits" chapter of the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus input receivers. The value of VREFSYS is system specific. In addition, to minimize VCC_CORE noise rejection from V R E F S Y S , i n c l u d e d e c o u p l i n g c a p a c i t o rs . Fo r m o re information, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. ZN and ZP Pins ZN (AC5) and ZP (AE5) are the push-pull compensation circuit pins. In Push-Pull mode (selected by the SIP parameter SysPushPull asserted), ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedance Z 0 of the transmission line. ZP is tied to VSS with a resistor that has a resistance matching the impedance Z0 of the transmission line. 74 Pin Descriptions Chapter 10 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 11 Ordering Information Standard AMD DuronTM Processor Model 7 Products AMD standard products are available in several operating ranges. The ordering part numbers (OPN) are formed by a combination of the elements, as shown in Figure 16. OPN D HD 1300 A M T 1 B Max FSB: B = 200 MHz Size of L2 Cache: 1 = 64 Kbytes Die Temperature: T = 90C Operating Voltage: M = 1.75V Package Type: A = CPGA Speed: 900 = 900 MHz, 950 = 950 MHz, 1000 =1000 MHz, 1100 =1100 MHz, 1200 = 1200 MHz, 1300 = 1300 MHz Generation: HD = High-Performance Desktop Processor Family/Architecture: D = AMD DuronTM Processor Model 7 Architecture Note: Spaces are added to the number shown above for viewing clarity only. Figure 16. OPN Example for the AMD DuronTM Processor Model 7 Chapter 11 Ordering Information 75 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 76 Ordering Information 24310G--January 2002 Chapter 11 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Appendix A Conventions and Abbreviations This section contains information about the conventions and abbreviations used in this document. Signals and Bits Active-Low Signals--Signal names containing a pound sign, such as SFILL#, indicate active-Low signals. They are asserted in their Low-voltage state and negated in their High-voltage state. When used in this context, High and Low are written with an initial upper case letter. Signal Ranges--In a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, D[63:0]). Reserved Bits and Signals--Signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. These bits and signals are reserved by AMD for future implementations. When software reads registers with reserved bits, the reserved bits must be masked. When software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. Three-State--In timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. Appendix A 77 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Invalid and Don't-Care--In timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. Data Terminology The following list defines data terminology: Quantities * A word is two bytes (16 bits) * A doubleword is four bytes (32 bits) * A quadword is eight bytes (64 bits) Addressing--Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. Abbreviations--The following notation is used for bits and bytes: * Kilo (K, as in 4-Kbyte page) * Mega (M, as in 4 Mbits/sec) * Giga (G, as in 4 Gbytes of memory space) Little-Endian Convention--The byte with the address xx...xx00 is in the least-significant byte position (little end). In byte diagrams, bit positions are numbered from right to left--the little end is on the right and the big end is on the left. Data structure diagrams in memory show low addresses at the bottom and high addresses at the top. When data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. Because byte addresses increase from right to left, strings appear in reverse order when illustrated. Bit Ranges--In text, bit ranges are shown with a dash (for example, bits 9-1). When accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, AD[31:0]). Bit Values--Bits can either be set to 1 or cleared to 0. Hexadecimal and Binary Numbers--Unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. See Table 23 on page 79 for more abbreviations. 78 Appendix A Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Abbreviations and Acronyms Table 23 contains the definitions of abbreviations used in this document. Table 23. Abbreviations Appendix A Abbreviation Meaning A Ampere F Farad G Giga- Gbit Gigabit Gbyte Gigabyte GHz Gigahertz H Henry h Hexadecimal K Kilo- Kbyte Kilobyte lbf Foot-pound M Mega- Mbit Megabit Mbyte Megabyte MHz Megahertz m Milli- ms Millisecond mW Milliwatt Micro- A Microampere F Microfarad H Microhenry s Microsecond V Microvolt n nano- nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm 79 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 23. Abbreviations (continued) Abbreviation Meaning p pico- pA picoampere pF picofarad pH picohenry ps picosecond s Second V Volt W Watt Table 24 contains the definitions of acronyms used in this document. Table 24. Acronyms 80 Abbreviation Meaning ACPI Advanced Configuration and Power Interface AGP Accelerated Graphics Port APCI AGP Peripheral Component Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input/Output System BIST Built-In Self-Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double-Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Direct Random Access Memory EIDE Enhanced Integrated Device Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In, First Out GART Graphics Address Remapping Table HSTL High-Speed Transistor Logic IDE Integrated Device Electronics ISA Industry Standard Architecture Appendix A Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 24. Acronyms (continued) Appendix A Abbreviation Meaning JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LAN Large Area Network LRU Least-Recently Used LVTTL Low Voltage Transistor Transistor Logic MSB Most Significant Bit MTRR Memory Type and Range Registers MUX Multiplexer NMI Non-Maskable Interrupt OD Open-Drain OPGA Organic Pin Grid Array PBGA Plastic Ball Grid Array PA Physical Address PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory Table PGA Pin Grid Array PLL Phase Locked Loop PMSM Power Management State Machine POS Power-On Suspend POST Power-On Self-Test RAM Random Access Memory ROM Read Only Memory RXA Read Acknowledge Queue SCSI Small Computer System Interface SDI System DRAM Interface SDRAM Synchronous Direct Random Access Memory SIMD Single Instruction Multiple Data SIP Serial Initialization Packet SMbus System Management Bus SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer 81 Preliminary Information AMD DuronTM Processor Model 7 Data Sheet 24310G--January 2002 Table 24. Acronyms (continued) 82 Abbreviation Meaning TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus ZDB Zero Delay Buffer Appendix A