Preliminary Information
AMD Duron
Processor Model 7essor Model 7
Data Sheetta Sheet
Publication # 24310 Rev: G
Issue Date: January 2002
TM
Preliminary Information
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, and 3DNow! are trademarks
of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Consortium.
MMX is a trademark of Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
© 2001, 2002 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Table of Contents iii
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 AMD Duron™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6
3 Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 13
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 26
7.4 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 27
7.5 VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 27
7.6 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7 VCC_CORE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.8 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.9 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 31
7.10 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 32
7.11 AMD Duron System Bus AC and DC Characteristics . . . . . . 34
7.12 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 36
7.13 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.14 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
7.15 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 41
iv Table of Contents
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
8 Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 43
8.1 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Signal Sequence and Timing Description . . . . . . . . . . . . . 43
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 46
8.2 Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 46
Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 CPGA Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 51
10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Duron System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . 68
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 68
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 68
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . 69
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 69
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 71
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . 72
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . 73
Table of Contents v
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Standard AMD Duron Processor Model 7 Products . . . . . . . . . . . . . 75
Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 77
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
vi Table of Contents
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
List of Figures vii
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
List of Figures
Figure 1. Typical AMD Duron™ Processor Model 7 System Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. AMD Duron Processor Model 7 Power Management States . . . 9
Figure 4. AMD Duron System Bus Disconnect Sequence in the
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 16
Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 32
Figure 10. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. General ATE Open Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 38
Figure 12. Signal Relationship Requirements During Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. AMD Duron Processor Model 7 CPGA Package . . . . . . . . . . . . 49
Figure 14. AMD Duron Processor Model 7 Pin Diagram—
Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 15. AMD Duron Processor Model 7 Pin Diagram—
Bottomside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 16. OPN Example for the AMD Duron Processor Model 7. . . . . . . 75
viii List of Figures
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
List of Tables ix
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
List of Tables
Table 1. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . 28
Table 7. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 32
Table 10. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 33
Table 11. AMD Duron™ System Bus DC Characteristics . . . . . . . . . . . . . 34
Table 12. AMD Duron System Bus AC Characteristics . . . . . . . . . . . . . . . 35
Table 13. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 39
Table 15. Guidelines for Platform Thermal Protection of the
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 41
Table 17. Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. Dimensions for the AMD Duron Processor Model 7
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 20. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 21. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 70
Table 22. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 74
Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 24. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
xList of Tables
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Revision History xi
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Revision History
Date Rev Description
January 2002 G
Changes for the AMD Duron™ Processor Model 7 Data Sheet since November 2001 include
the following:
■In Chapter 6, revised Table 1, “Thermal Design Power,” on page 23
■In Chapter 7, revised Table 8, “VCC_CORE Voltage and Current,” on page 31 and Table 11,
“AMD Duron™ System Bus DC Characteristics,” on page 34
■IN Chapter 11, revised Figure 16, "OPN Example for the AMD Duron™ Processor Model 7‚"
on page 75
November 2001 F
Changes for the AMD Duron™ Processor Model 7 Data Sheet since October 2001 include the
following:
■In Chapter 6, revised Table 1, “Thermal Design Power,” on page 23
■In Chapter 7, revised Table 6, “VCC_CORE AC and DC Characteristics,” on page 28, revised
Table 8, “VCC_CORE Voltage and Current,” on page 31, revised Table 13, “General AC and
DC Characteristics,” on page 36, added new section, “Open Drain Test Circuit” on page 38,
added Figure 11, "General ATE Open Drain Test Circuit‚" on page 38, added new section,
“Thermal Protection Characterization” on page 40, and added Table 15, “Guidelines for
Platform Thermal Protection of the Processor,” on page 41
■In Chapter 11, revised Figure 16, "OPN Example for the AMD Duron™ Processor Model 7‚"
on page 75
October 2001 E
Changes for the AMD Duron™ Processor Model 7 Data Sheet since September 2001 include
the following:
■In Chapter 8, revised “Power-Up Timing Requirements” on page 44, and “Clock Multiplier
Selection (FID[3:0])” on page 46
■In Chapter 10, revised “FID[3:0] Pins” on page 70
September 2001 D
Changes for the AMD Duron™ Processor Model 7 Data Sheet include the following:
■In Chapter 6, updated Table 1, “Thermal Design Power,” on page 23
■In Chapter 7, updated Table 8, “VCC_CORE Voltage and Current,” on page 31 and revised
Table 16, “APIC Pin AC and DC Characteristics,” on page 41
■In Chapter 11, updated Figure 16, "OPN Example for the AMD Duron™ Processor Model 7‚"
on page 75
September 2001 C In Chapter 7, revised Figure 8, "VCC_CORE Voltage Waveform‚" on page 29 .
August 2001 B Initial release of the AMD Duron™ Processor Model 7 Data Sheet.
xii Revision History
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 1 Overview 1
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
1 Overview
The AMD Duron™ processor model 7 enables an optimized PC
solution for value-conscious business and home users by providing
the capability and flexibility to meet their computing needs for both
today and tomorrow.
The AMD Duron processor model 7 is the latest offering from
AMD designed for the value segment of the market. The
innovative design was developed to accommodate new and
more advanced applications, meeting the requirements of
today's most demanding value-conscious buyers without
compromising their budget.
Delivered in a CPGA package, the AMD Duron processor model
7 is the new AMD workhorse processor for value desktop
systems, delivering an extremely high integer, floating-point,
and 3-D multimedia performance for applications running on
x86 system platforms. The AMD Duron processor model 7
provides value-conscious customers with access to advanced
technology that allows their system investment to last for years
to come. The AMD Duron processor model 7 is designed as a
solid platform for surfing the Internet, digital entertainment,
and personal creativity. In addition, it is engineered to enable
superior business productivity by delivering an optimized
combination of computing performance and value.
The AMD Duron processor features a seventh-generation
microarchitecture with an integrated, exclusive L2 cache, which
supports the growing processor and system bandwidth
requirements of emerging software, graphics, I/O, and memory
technologies. The high-speed execution core of the AMD Duron
processor includes multiple x86 instruction decoders, a
dual-ported 128-Kbyte split level-one (L1) cache, an exclusive
64-Kbyte L2 cache, three independent integer pipelines, three
address calculation pipelines, and a superscalar, fully
pipelined, out-of-order, three-way floating-point engine. The
floating-point engine is capable of delivering outstanding
performance on numerically complex applications.
The AMD Duron processor model 7 microarchitecture
incorporates 3DNow!™ Professional technology, a
high-performance cache architecture, and a 200-MHz,
1.6-Gigabyte per second system bus. The AMD Duron system
2Overview Chapter 1
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
bus combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.
The AMD Duron processor model 7 is binary-compatible with
existing x86 software and backwards compatible with
applications optimized for MMX™ and 3DNow! technology.
Using a data format and Single-Instruction Multiple-Data
(SIMD) operations based on the MMX instruction model, the
AMD Duron processor can produce as many as four 32-bit,
single-precision floating-point results per clock cycle. The
3DNow! Professional technology implemented in the
AMD Duron processor model 7 includes new integer
multimedia instructions and software-directed data movement
instructions for optimizing such applications as digital content
creation and streaming video for the Internet, as well as new
instructions for Digital Signal Processing
(DSP)/communications applications.
1.1 Microarchitecture Summary
The following features summarize the AMD Duron processor
model 7 microarchitecture:
■An advanced nine-issue, superpipelined, superscalar x86
processor microarchitecture designed for high clock
frequencies
■Multiple x86 instruction decoders
■Fully pipelined, floating-point unit that executes all x87
(floating-point), MMX and 3DNow! Professional technology
instructions
■Three out-of-order, superscalar, pipelined integer units
■Three out-of-order, superscalar, pipelined address
calculation units
■A 72-entry instruction control unit
■Advanced dynamic branch prediction
■A 200-MHz AMD Duron system bus (scalable beyond 400
MHz) enabling leading-edge system bandwidth for data
movement-intensive applications
■High-performance cache architecture featuring an
integrated 128-Kbyte L1 cache and an exclusive 64-Kbyte L2
cache
Chapter 1 Overview 3
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
The AMD Duron processor delivers excellent system
performance in a cost-effective, industry-standard form factor.
The AMD Duron processor is compatible with motherboards
based on Socket A.
Figure 1 shows a typical AMD Duron processor system block
diagram.
Figure 1. Typical AMD Duron™ Processor Model 7 System Block Diagram
SDRAM or DDR
AGP Bus
Memory Bus
AGP
PCI Bus
LAN SCSI
LPC Bus
USB
Dual EIDE
AM D Dur on™
Processor Model 7
System Controller
(Northbridge)
Peripheral Bus
Controller
(Southbridge)
Modem / Audio
Thermal Monitor
BIOS
AMD Duron System Bus
4Overview Chapter 1
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 2 Interface Signals 5
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
2 Interface Signals
2.1 Overview
The AMD Duron™ system bus architecture is designed to
deliver excellent data movement bandwidth for next-
generation x86 platforms as well as the high-performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 72-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Duron™ System Bus Signals”
on page 6, Chapter 10, “Pin Descriptions” on page 51, and the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
2.2 Signaling Technology
The AMD Duron system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
“Pin Descriptions” on page 51.
6Interface Signals Chapter 2
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
2.3 Push-Pull (PP) Drivers
The AMD Duron processor model 7 supports Push-Pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 74 for more information.
2.4 AMD Duron™ System Bus Signals
The AMD Duron system bus is a clock-forwarded, point-to-point
interface with the following three point-to-point channels:
■A 13-bit unidirectional output address/command channel
■A 13-bit unidirectional input address/command channel
■A 72-bit bidirectional data channel
For more information, see Chapter 7, “Electrical Data” on page
25 and the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902.
Chapter 3 Logic Symbol Diagram 7
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
3 Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and output
signals.
Figure 2. Logic Symbol Diagram
SDATA[63:0]#
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
Data
SADDIN[14:2]#
SADDINCLK#
Probe/SysCMD
SADDOUT[14:2]#
SADDOUTCLK#
VID[4:0]
FID[3:0]
A20M#
CLKFWDRST
CONNECT
COREFB
COREFB#
FERR
IGNNE#
INIT#
INTR
NMI
PROCRDY
PWROK
RESET#
SFILLVALID#
SMI#
STPCLK#
SYSCLK#SYSCLK
Clock
Voltage
Control
Frequency
Control
Legacy
Request
AMD Duron™
Processor Model 7
SDATAINVALID#
SDATAOUTVALID#
Power
and Initialization
Management Thermal
Diode
THERMDA
THERMDC
FLUSH#
PICCLK
PICD[1:0] APIC
8Logic Symbol Diagram Chapter 3
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 4 Power Management 9
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
4 Power Management
This chapter describes the power management control system
of the AMD Duron™ processor model 7. The power
management features of the processor are compliant with the
ACPI 1.0b and ACPI 2.0 specifications.
4.1 Power Management States
The AMD Duron processor model 7 supports low-power Halt
and Stop Grant states. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating
systems for processor power management.
Figure 3 shows the power management states of the processor.
The figure includes the ACPI “Cx” naming convention for these
states.
Figure 3. AMD Duron™ Processor Model 7 Power Management States
C1
Halt
C0
Working4
Execute HLT
SMI#, INTR, NMI, INIT#, RESET#
Incoming Probe
Probe Serviced
STPCLK# asserted
STPCLK# asserted
2
STPCLK# deasserted
3
C2
Stop Grant
Cache Snoopable
Incoming Probe
Probe Serviced
Probe
State1
STPCLK# deasserted
(Read PLVL2 register
or throttling)
S1
Stop Grant
Cache Not Snoopable
Sleep
STPCLK# asserted
STPCLK#deasserted
Note: The AMD DuronTM System Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
Software transitions
Hardware transitions
Legend
10 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
The following sections provide an overview of the power
management states. For more details, refer to the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
Note: In all power management states that the processor is
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
Working State The Working state is the state in which the processor is
executing instructions.
Halt State When the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Duron system bus. The processor only enters the low
power state dictated by the CLK_Ctl MSR if the system
controller (Northbridge) disconnects the AMD Duron system
bus in response to the Halt special cycle.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR
or NMI pins, or via a local APIC interrupt message. When the
Halt state is exited, the processor will initiate an AMD Duron
system bus connect if it is disconnected.
Stop Grant States The processor enters the Stop Grant state upon recognition of
assertion of STPCLK# input. After entering the Stop Grant
state, the processor issues a Stop Grant special bus cycle on the
AMD Duron system bus. The processor is not in a low-power
state at this time, because the AMD Duron system bus is still
connected. After the Northbridge disconnects the AMD Duron
system bus in response to the Stop Grant special bus cycle, the
processor enters a low-power state dictated by the CLK_Ctl
MSR. If the Northbridge needs to probe the processor during
the Stop Grant state while the system bus is disconnected, it
Chapter 4 Power Management 11
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
must first connect the system bus. Connecting the system bus
places the processor into the higher power probe state. After
the Northbridge has completed all probes of the processor, the
Northbridge must disconnect the AMD Duron system bus again
so that the processor can return to the low-power state. During
the Stop Grant states, the processor latches INIT#, INTR, NMI,
SMI#, or a local APIC interrupt message, if they are asserted.
The Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
deasserted, the processor initiates a connect of the AMD Duron
system bus if it is disconnected. After the processor enters the
Working state, any pending interrupts are recognized and
serviced and the processor resumes execution at the instruction
boundary where STPCLK# was initially recognized. If RESET#
is sampled asserted during the Stop Grant state, the processor
exits the Stop Grant state and the reset process begins.
There are two mechanisms for asserting STPCLK#—hardware
and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This is accomplished by asserting the THERM#
input to the Southbridge. Throttling asserts STPCLK# for a
percentage of a predefined throttling period: STPCLK# is
repetitively asserted and deasserted until THERM# is
deasserted.
Software can force the processor into the Stop Grant state by
accessing ACPI-defined registers typically located in the
Southbridge.
The operating system places the processor into the C2 Stop
Grant state by reading the P_LVL2 register in the Southbridge.
If an ACPI Thermal Zone is defined for the processor, the
operating system can initiate throttling with STPCLK# using
the ACPI defined P_CNT register in the Southbridge. The
Northbridge connects the AMD Duron system bus, and the
processor enters the Probe state to service cache snoops during
Stop Grant for C2 or throttling.
In C2, probes are allowed, as shown in Figure 3 on page 9
12 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State The Probe state is entered when the Northbridge connects the
AMD Duron system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Duron system bus again.
Chapter 4 Power Management 13
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
4.2 Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Duron system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Duron system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
Northbridge asserts CLKFWDRST in anticipation of
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Duron system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
14 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor sends the
Connect special cycle to the Northbridge, rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
Chapter 4 Power Management 15
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Figure 4 shows STPCLK# assertion resulting in the processor in
the Stop Grant state and the AMD Duron system bus
disconnected.
Figure 4. AMD Duron™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Duron system bus disconnect sequence
is as follows:
1. The peripheral controller (Southbridge) asserts STPCLK#
to place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters
the Stop Grant state and then issues a Stop Grant special
cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending,
initiating a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge passes
the Stop Grant special cycle along to the Southbridge.
Stop Grant
Stop Grant
STPCLK#
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
AMD Duron™
System Bus
16 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Duron system bus, and puts the processor into the
Working state.
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
STPCLK #
PROCRDY
CONNECT
CLKFWDRST
Chapter 4 Power Management 17
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Connect State
Diagram
Figure 6 below and Figure 7 on page 18 show the Northbridge
and processor connect state diagrams, respectively.
Figure 6. Northbridge Connect State Diagram
Condition
1 A disconnect is requested and probes are still pending.
2 A disconnect is requested and no probes are pending.
3 A Connect special cycle from the processor.
4 No probes are pending.
5 PROCRDY is deasserted.
6 A probe needs service.
7 PROCRDY is asserted.
8
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Action
ADeassert CONNECT eight SYSCLK periods
after last SysDC sent.
BAssert CLKFWDRST.
C Assert CONNECT.
D Deassert CLKFWDRST.
Disconnect
Pending Connect Disconnect
Requested
Reconnect
Pending
Probe
Pending 2
Disconnect
Probe
Pending 1
1
3
2/A
4/A
5/B
3/C
7/D,C
8
6/C 7/D
8
18 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Figure 7. Processor Connect State Diagram
Condition
1CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
2Processor receives a wake-up event and must cancel
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
4Processor wake-up event or CONNECT asserted by
Northbridge.
5 CLKFWDRST is deasserted by the Northbridge.
6Forward clocks start three SYSCLK periods after
CLKFWDRST is deasserted.
Action
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
CReturn internal clocks to full speed and assert
PROCRDY.
Note:
* The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Duron™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Connect
Disconnect
Pending
Disconnect
Connect
Pending 1
Connect
Pending 2
1
3/A
4/C
5
6/B
2/B
Chapter 4 Power Management 19
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
4.3 Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Duron system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
20 Power Management Chapter 4
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 5 CPUID Support 21
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
5 CPUID Support
AMD Duron™ processor model 7 version and feature set
recognition can be performed through the use of the CPUID
instruction, that provides complete information about the
processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information on the use of the CPUID instruction see the
following documents:
■AMD Processor Recognition Application Note, order# 20734
■AMD Athlon™ Processor Recognition Application Note
Addendum, order# 21922
■AMD Athlon™ and AMD Duron™ Processors BIOS, Software,
and Debug Developers Guide, order# 21656
22 CPUID Support Chapter 5
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 6 Thermal Design 23
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
6 Thermal Design
The AMD Duron™ processor model 7 provides a diode that can
be used in conjunction with an external temperature sensor to
determine the die temperature of the processor.
The diode anode (THERMDA) and cathode (THERMDC) are
available as pins on the processor.
Refer to “THERMDA and THERMDC Pins” on page 73 for
more details.
For information about thermal design for the AMD Duron
processor model 7, including layout and airflow considerations,
see the AMD Athlon™ Processor Thermal, Mechanical, and
Chassis Cooling Design Guide, order# 23794, and the cooling
guidelines on http://www.amd.com.
Table 1 shows the thermal design power specifications for the
AMD Duron processor model 7.
Table 1. Thermal Design Power
Frequency
(MHz)
Nominal
Voltage
Maximum Thermal
Power
Typical Thermal
Power
Max Die
Temperature
900
1.75 V
42.7 W 39.2 W
90ºC
950 44.4 W 40.8 W
1000 46.1 W 42.4 W
1100 50.3 W 46.2 W
1200 54.7 W 50.3 W
1300 60.0 W 55.2 W
Note:
The thermal design power represents the maximum sustained power dissipated while
executing publicly available software or instruction sequences under normal system
operation at nominal VCC_CORE. Thermal solutions must monitor the processor temperature
to prevent the processor from exceeding its maximum die temperature.
24 Thermal Design Chapter 6
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 7 Electrical Data 25
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
7 Electrical Data
7.1 Conventions
The conventions used in this chapter are as follows:
■Current specified as being sourced by the processor is
negative.
■Current specified as being sunk by the processor is positive.
7.2 Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 2 defines each group and the signals contained in each
group.
Table 2. Interface Signal Groupings
Signal Group Signals Notes
Power VID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “Absolute Ratings” on page 30,
“Voltage Identification (VID[4:0])”
on page 26, “VID[4:0] Pins” on page
73, “” on page 27,“VCCA Pin” on
page 73, and “COREFB and
COREFB# Pins” on page 69.
Frequency FID[3:0]
See “Frequency Identification
(FID[3:0])” on page 27 and
“FID[3:0] Pins” on page 70.
System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#),
PLLBYPASSCLK#, PLLBYPASSCLK
See Table 9, “SYSCLK and SYSCLK#
DC Characteristics,” on page 32,
Table 10, “SYSCLK and SYSCLK# AC
Characteristics,” on page 33,
“SYSCLK and SYSCLK#” on page
73, and “PLL Bypass and Test Pins”
on page 72.
AMD Duron™
System Bus
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#,
SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#,
SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY,
CONNECT
See “AMD Duron™ System Bus AC
and DC Characteristics” on page 34,
and “CLKFWDRST Pin” on page 68.
26 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.3 Voltage Identification (VID[4:0])
Table 3 shows the VID[4:0] DC Characteristics. For more infor-
mation on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on
page 73.
Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#,
STPCLK#, FLUSH#
See “General AC and DC
Characteristics” on page 36, “INTR
Pin” on page 71, “NMI Pin” on page
72, “SMI# Pin” on page 72, “INIT#
Pin” on page 71, “A20M# Pin” on
page 68, “FERR Pin” on page
69,“IGNNE# Pin” on page 71,
“SYSCLK and SYSCLK#” on page
73, and “FLUSH# Pin” on page 71.
JTAG TMS, TCK, TRST#, TDI, TDO See “General AC and DC
Characteristics” on page 36.
Test PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1,
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC
Characteristics” on page 36, “PLL
Bypass and Test Pins” on page 72,
“Scan Pins” on page 72, “Analog
Pin” on page 68.
Miscellaneous DBREQ#, DBRDY, PWROK
See “General AC and DC
Characteristics” on page 36,
“DBRDY and DBREQ# Pins” on
page 69, “PWROK Pin” on page 72.
APIC PICD[1:0]#, PICCLK
See “APIC Pins AC and DC
Characteristics” on page 41, and
“APIC Pins, PICCLK, PICD[1:0]#” on
page 68.
Thermal THERMDA, THERMDC
Table 14, “Thermal Diode Electrical
Characteristics,” on page 39, and
“THERMDA and THERMDC Pins”
on page 73
Table 2. Interface Signal Groupings (continued)
Signal Group Signals Notes
Table 3. VID[4:0] DC Characteristics
Parameter Description Min Max
IOL Output Current Low 16 mA
VOH Output High Voltage – 2.625 V*
Note:
* The VID pins must not be pulled above this voltage by an external pullup resistor.
Chapter 7 Electrical Data 27
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
7.4 Frequency Identification (FID[3:0])
Table 4 shows the FID[3:0] DC characteristics. For more
information, see “FID[3:0] Pins” on page 70.
7.5 VCCA AC and DC Characteristics
Table 5 shows the AC and DC characteristics for VCCA. For
more information, see “VCCA Pin” on page 73.
7.6 Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design
Guide, order# 24363, or contact your local AMD office for
information about the decoupling required on the motherboard
for use with the AMD Duron™ processor model 7.
Table 4. FID[3:0] DC Characteristics
Parameter Description Min Max
IOL Output Current Low 16 mA
VOH Output High Voltage – 2.625 V *
Note:
* The FID pins must not be pulled above this voltage by an external pullup resistor.
Table 5. VCCA AC and DC Characteristics
Symbol Parameter Min Nominal Max Units Notes
VVCCA VCCA Pin Voltage 2.25 2.5 2.75 V 1
IVCCA VCCA Pin Current 0 50 mA/GHz 2
Notes:
1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.
2. Measured at 2.5 V.
28 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.7 VCC_CORE Characteristics
Table 6 shows the AC and DC characteristics for VCC_CORE.
The VCC_CORE nominal value is shown in Table 8,
“VCC_CORE Voltage and Current,” on page 31. See Figure 8 on
page 29 for a graphical representation of the VCC_CORE
waveform.
Table 6. VCC_CORE AC and DC Characteristics
Symbol Parameter Limit in Working State Units
VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM*50 mV
VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM*–50 mV
VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM*150 mV
VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM*–100 mV
tMAX_AC Maximum excursion time for AC transients 10 µs
tMIN_AC Negative excursion time for AC transients 5 µs
Note:
*All voltage measurements are taken differentially at the COREFB/COREFB# pins.
Chapter 7 Electrical Data 29
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Figure 8 shows the processor core voltage (VCC_CORE)
waveform response to perturbation. The tMIN_AC (negative AC
transient excursion time) and tMAX_AC (positive AC transient
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
Figure 8. VCC_CORE Voltage Waveform
tmin_AC
VCC_CORE_MAX_AC
tmax_AC
VCC_CORE_MAX_DC
VCC_CORE_NOM
VCC_CORE_MIN_DC
VCC_CORE_MIN_AC
ICORE_MIN
ICORE_MAX
dI /dt
30 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.8 Absolute Ratings
The AMD Duron processor model 7 should not be subjected to
conditions exceeding the absolute ratings, as such conditions
can adversely affect long-term reliability or result in functional
damage.
Table 7 lists the maximum absolute ratings of operation for the
AMD Duron processor.
Table 7. Absolute Ratings
Parameter Description Min Max
VCC_CORE AMD Duron™ Processor Model 7 core supply –0.5 V VCC_CORE Max + 0.5 V
VCCA AMD Duron Processor Model 7 PLL supply –0.5 V VCCA Max + 0.5 V
VPIN Voltage on any signal pin –0.5 V VCC_CORE Max + 0.5 V
TSTORAGE Storage temperature of processor –40ºC 100ºC
Chapter 7 Electrical Data 31
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
7.9 VCC_CORE Voltage and Current
Table 8 shows the voltage and current for the AMD Duron
processor model 7 during normal and reduced power states.
Table 8. VCC_CORE Voltage and Current
Frequency
(MHz)
Nominal
Voltage
Die
Temperature
ICC (Processor Current)
Typical Max
900
1.75 90°C
22.4 A 24.4 A
950 23.3 A 25.4 A
1000 24.2 A 26.3 A
1100 26.4 A 28.7 A
1200 28.7 A 31.3 A
1300 31.5 A 34.3 A
Stop Grant S1 or
Sleep State1, 2, 3, 4, 5 1.30 V 50°C 0.66 A 1.54 A
Notes:
1. The cooling fan can be turned off during the Sleep State, but customers should test their
systems in Sleep state to ensure that the system, when using typical parts, has adequate
cooling (without the fan during the Sleep State) to meet the temperature specification of the
product.
2. See Figure 3, "AMD Duron™ Processor Model 7 Power Management States" on page 9.
3. The maximum Stop Grant currents are absolute worst case currents for parts that may yield
from the worst case corner of the process and are not representative of the typical Stop Grant
current that is currently about one-third of the maximum specified current.
4. These currents occur when the AMD Duron™ System Bus is disconnected and a low power
ratio of 1/64 is applied to the core clock grid of the processor as dictated by a value of
6003_D22Fh programmed into the Clock Control (CLK_Ctl) MSR.
5. The Stop Grant current consumption is characterized and not tested.
32 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.10 SYSCLK and SYSCLK# AC and DC Characteristics
Table 9 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together.
Figure 9 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
Figure 9. SYSCLK and SYSCLK# Differential Clock Signals
Table 9. SYSCLK and SYSCLK# DC Characteristics
Symbol Description Min Max Units
VThreshold-DC Crossing before transition is detected (DC) 400 mV
VThreshold-AC Crossing before transition is detected (AC) 450 mV
ILEAK_P Leakage current through P-channel pullup to VCC_CORE –1 mA
ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) 1 mA
VCROSS Differential signal crossover VCC_CORE/2±100 mV
CPIN Capacitance* 4 12* pF
Note:
* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
VCROSS VThreshold-DC = 400mV VThreshold-AC = 450mV
Chapter 7 Electrical Data 33
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Table 10 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of the AMD Duron processor model 7.
Figure 10 shows a sample waveform of the SYSCLK signal.
Figure 10. SYSCLK Waveform
Table 10. SYSCLK and SYSCLK# AC Characteristics
Symbol Parameter Description Minimum Maximum Units Notes
Clock Frequency 50 100 MHz
Duty Cycle 30% 70% –
t1Period 10 ns 1, 2
t2High Time 1.8 ns
t3Low Time 1.8 ns
t4Fall Time 2.0 ns
t5Rise Time 2.0 ns
Period Stability ± 300 ps
Notes:
1. Circuitry driving the AMD Duron™ system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the
PLL to track the jitter. The –20dB attenuation point, as measured into a 10- or 20-pF load must be less than 500 kHz.
2. Circuitry driving the AMD Duron system bus clock inputs may purposely alter the AMD Duron system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Duron system bus period violate the minimum specification above.
AMD Duron system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
t5
VCROSS
t2
t3
t4
t1
VThreshold-AC
34 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.11 AMD Duron™ System Bus AC and DC Characteristics
Table 11 shows the DC characteristics of the AMD Duron
system bus used by the AMD Duron processor model 7. See
Table 6, “VCC_CORE AC and DC Characteristics,” on page 28
for information on TDIE and VCC_CORE. For information about
SYSCLK and SYSCLK#, see “SYSCLK and SYSCLK#” on page
73 and Table 19, “Pin Name Abbreviations,” on page 54.
Table 11. AMD Duron™ System Bus DC Characteristics
Symbol Parameter Condition Min Max Units Notes
VREF DC Input Reference Voltage (0.5*VCC_CORE)
–50
(0.5*VCC_CORE)
+50 mV 1
IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal –200 µA
IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal 100 µA
VIH Input High Voltage VREF + 200 VCC_CORE +
500 mV
VIL Input Low Voltage –500 VREF – 200 mV
VOH Output High Voltage IOUT = –200 µA0.85 VCC_CORE VCC_CORE+500 mV 2
VOL Output Low Voltage IOUT = 1 mA –500 400 mV 2
ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) –1 mA
ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE
Nominal 1mA
CIN Input Pin Capacitance 4 12 pF
Notes:
1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed above.
2. Specified at the TDIE and VCC_CORE specifications in this document.
Chapter 7 Electrical Data 35
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
The AC characteristics of the AMD Duron system bus are shown
in Table 12 on page 35. The parameters are grouped based on
the source or destination of the signals involved.
Table 12. AMD Duron™ System Bus AC Characteristics
Group Symbol Parameter Min Max Units Notes
All Signals TRISE Output Rise Slew Rate 1 3 V/ns 1
TFALL Output Fall Slew Rate 1 3 V/ns 1
Forward
Clocks
TSKEW-SAMEEDGE Output skew with respect to
the same clock edge –385ps2
TSKEW-DIFFEDGE Output skew with respect to a
different clock edge – 770 ps 2
TSU Input Data Setup Time 300 ps 3
THD Input Data Hold Time 300 ps 3
CIN Capacitance on input Clocks 4 12 pF
COUT Capacitance on output Clocks 4 12 pF
Sync
TVAL RSTCLK to Output Valid 250 2000 ps 4, 5
TSU Setup to RSTCLK 500 ps 4, 6
THD Hold from RSTCLK 1000 ps 4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
36 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.12 General AC and DC Characteristics
Table 13 shows the AMD Duron processor model 7 AC and DC
characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
Table 13. General AC and DC Characteristics
Symbol Parameter Description Condition Min Max Units Notes
VIH Input High Voltage (VCC_CORE/2) +
200 mV
VCC_CORE +
300 mV V1,2
VIL Input Low Voltage –300 350 mV 1, 2
VOH Output High Voltage VCC_CORE –
400
VCC_CORE +
300 mV
VOL Output Low Voltage –300 400 mV
ILEAK_P Tristate Leakage Pullup VIN = VSS
(Ground) –1 mA
ILEAK_N Tristate Leakage Pulldown VIN = VCC_CORE
Nominal 600 µA
IOH Output High Current –16 mA 3
IOL Output Low Current 16 mA 3
TSU Sync Input Setup Time 2.0 ns 4, 5
THD Sync Input Hold Time 0.0 ps 4, 5
TDELAY Output Delay with respect to RSTCLK 0.0 6.1 ns 5
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE minimum and VCC_CORE maximum.
3. IOL and IOH are measured at VOL max and VOH min, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power-Up Timing Requirements,“ for more
information.
Chapter 7 Electrical Data 37
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
TBIT Input Time to Acquire 20.0 ns 7, 8
TRPT Input Time to Reacquire 40.0 ns 9–13
TRISE Signal Rise Time 1.0 3.0 V/ns 6
TFALL Signal Fall Time 1.0 3.0 V/ns 6
CPIN Pin Capacitance 4 12 pF
TVALID Time to data valid 100 ns 14
Table 13. General AC and DC Characteristics (continued)
Symbol Parameter Description Condition Min Max Units Notes
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE minimum and VCC_CORE maximum.
3. IOL and IOH are measured at VOL max and VOH min, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power-Up Timing Requirements,“ for more
information.
38 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
7.13 Open Drain Test Circuit
Figure 11 is a test circuit that may be used on Automated Test
Equipment (ATE) to test for validity on open drain pins.
Refer to Table 13, “General AC and DC Characteristics,” on
page 36 for timing requirements.
Figure 11. General ATE Open Drain Test Circuit
Open Drain Pin
VTermination1
50 Ω ±3%
IOL = Output Current2
Notes:
1. VTermination = 1.2 V for VID and FID pins
VTermination = 1.0 V for APIC pins
2. IOL = –16 mA for VID and FID pins
IOL = –12 mA for APIC pins
Chapter 7 Electrical Data 39
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
7.14 Thermal Diode Characteristics
Thermal Diode Electrical Characteristics. Table 14 shows the
AMD Duron processor model 7 electrical characteristics of the
on-die thermal diode.
Table 14. Thermal Diode Electrical Characteristics
Symbol Parameter Description Min Nom Max Units Notes
Ifw Forward bias current 5 300 µA 1
n Diode ideality factor 1.002 1.008 1.016 2, 3, 4, 5
Notes:
1. The sourcing current should always be used in forward bias only.
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA.
3. Not 100% tested. Specified by design and limited characterization.
4. The diode ideality factor, n, is a correction factor to the ideal diode equation.
For the following equations, use the following variables and constants:
nDiode ideality factor
kBoltzmann constant
qElectron charge constant
TDiode temperature (Kelvin)
VBE Voltage from base to emitter
ICCollector current
ISSaturation current
NRatio of collector currents
The equation for VBE is:
By sourcing two currents and using the above equation, a difference in base emitter voltage
can be found that leads to the following equation for temperature:
5. If a different sourcing current pair is used other than 10 µA and 100 µA, the following equation
should be used to correct the temperature. Subtract this offset from the temperature measured
by the temperature sensor.
For the following equations, use the following variables and constants:
Ihigh High sourcing current
Ilow Low sourcing current
Toffset (in °C) can be found using the following equation:
VBE
nkT
q
--------- IC
IS
-----
èø
æö
ln⋅=
T∆VBE
nN()ln k
q
---⋅⋅
-----------------------------
=
Toffset 6.0 104
⋅()
Ihigh Ilow
–()
Ihigh
Ilow
-----------
èø
æö
ln
--------------------------------⋅2.34–=
40 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Thermal Protection Characterization. The following section describes
parameters relating to thermal protection. The implementation
of thermal control circuitry to control processor temperature is
left to the manufacturer to determine how to implement.
Thermal limits in motherboard design are necessary to protect
the processor from thermal damage. TSHUTDOWN is the
temperature for thermal protection circuitry to initiate
shutdown of the processor. TSD_DELAY is the maximum time
allowed from the detection of the over-temperature condition to
processor shutdown to prevent thermal damage to the
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by TSD_DELAY can
cause thermal damage to the processor during the unlikely
events of fan failure or powering up the processor without a
heat-sink. The processor relies on thermal circuitry on the
motherboard to turn off the regulated core voltage to the
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
■AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363
■Thermal Diode Monitoring Circuits, order# 25658
■AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
■http://www1.amd.com/products/athlon/thermals
Table 15 on page 41 shows the TSHUTDOWN and TSD_DELAY
specifications for circuitry in motherboard design necessary for
thermal protection of the processor.
Chapter 7 Electrical Data 41
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
7.15 APIC Pins AC and DC Characteristics
Table 16 shows the AMD Duron processor model 7 AC and DC
characteristics of the APIC pins.
Table 15. Guidelines for Platform Thermal Protection of the Processor
Symbol Parameter Description Max Units Notes
TSHUTDOWN Thermal diode shutdown temperature for processor protection 125 °C1, 2, 3
TSD_DELAY Maximum allowed time from TSHUTDOWN detection to processor shutdown 500 ms 1, 3
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The AMD Duron™ processor model 7 provides a thermal diode for measuring die temperature of the processor. The processor
relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal
shutdown event. Refer to Thermal Diode Monitoring Circuits, order# 25658, for thermal protection circuitry designs.
Table 16. APIC Pin AC and DC Characteristics
Symbol Parameter Description Condition Min Max Units Notes
VIH Input High Voltage 1.7 2.625 V 1, 3
VIL Input Low Voltage –300 700 mV 1, 2
VOH Output High Voltage 2.625 V 3
VOL Output Low Voltage –300 400 mV
ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) –1 mA
ILEAK_N Tristate Leakage Pulldown VIN = 2.5 V 1mA
IOL Output Low Current VOL Max 12 mA
TRISE Signal Rise Time 1.0 3.0 V/ns 4
TFALL Signal Fall Time 1.0 3.0 V/ns 4
CPIN Pin Capacitance 4 12 pF
Notes:
1. Characterized across DC supply voltage range
2. 2.625 V = 2.5 V + 5% maximum
3. Edge rates indicate the range over which inputs were characterized
42 Electrical Data Chapter 7
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 8 Signal and Power-Up Requirements 43
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
8 Signal and Power-Up Requirements
The AMD Duron™ processor model 7 is designed to provide
functional operation if the voltage and temperature parameters
are within the limits of normal operating ranges.
8.1 Power-Up Requirements
Signal Sequence and
Timing Description
Figure 12 shows the relationship between key signals in the
system during a power-up sequence. This figure details the
requirements of the processor.
Figure 12. Signal Relationship Requirements During Power-Up Sequence
Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
2. Requirements 1-8 in Figure 12 are described in “Power-Up Timing Requirements” on page
44.
3.3 V Supply
VCCA (2.5 V)
(for PLL)
RESET#
VCC_CORE
(Processor Core)
NB_RESET#
PWROK
System Clock
2
1
3
4
5
6
FID[3:0]
78
Warm reset
condition
44 Signal and Power-Up Requirements Chapter 8
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Power-Up Timing Requirements.
The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Duron processor model 7 does not set the correct
clock multiplier if PWROK is asserted prior to a RESET#
assertion. It is recommended that RESET# be asserted at
least 10 nanoseconds prior to the assertion of PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is deasserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that VCC_CORE and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, VCC_CORE, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Duron processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, VCC_CORE, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
Chapter 8 Signal and Power-Up Requirements 45
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Table 13, “General AC and DC
Characteristics,” on page 36. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
46 Signal and Power-Up Requirements Chapter 8
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct Serial Initialization Packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Duron system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information, see “FID[3:0] Pins” on page 70.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
8.2 Processor Warm Reset Requirements
Northbridge Reset
Pins
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
Chapter 9 Mechanical Data 47
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
9 Mechanical Data
9.1 Introduction
The AMD Duron™ processor model 7 connects to the
motherboard through a Pin Grid Array (PGA) socket named
Socket A and utilizes the Ceramic Pin Grid Array (CPGA)
package type described in “CPGA Package Description” on
page 48. For more information, see the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363.
9.2 Die Loading
The processor die on the CPGA package is exposed at the top of
the package. This feature facilitates heat transfer from the die
to an approved heat sink. It is critical that the mechanical
loading of the heat sink does not exceed the limits shown in
Table 17. Any heat sink design should avoid loads on corners
and edges of die. The CPGA package has compliant pads that
serve to bring surfaces in planar contact. Tool-assisted zero
insertion force sockets should be designed so that no load is
placed on the ceramic substrate of the package.
Table 17 shows the mechanical loading specifications for the
processor die.
Table 17. Mechanical Loading
Location Dynamic (MAX) Static (MAX) Units Note
Die Surface 100 30 lbf 1
Die Edge 10 10 lbf 2
Notes:
1. Load specified for coplanar contact to die surface.
2. Load defined for a surface at no more than a two degree angle of inclination to die surface.
48 Mechanical Data Chapter 9
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
9.3 CPGA Package Description
Figure 13 on page 49 shows a diagram and notes for the
AMD Duron processor model 7 CPGA package. Table 18
provides the dimensions in millimeters assigned to the letters
and symbols shown in the Figure 13 diagram.
Table 18. Dimensions for the AMD Duron™ Processor Model 7 CPGA
Package
Letter or
Symbol
Minimum
Dimension1
Maximum
Dimension1
Letter or
Symbol
Minimum
Dimension1
Maximum
Dimension1
D/E 49.27 49.78 E9 1.66 1.96
D1/E1 45.72 BSC G/H — 4.50
D2 11.698 REF A 2.24 REF
D3 3.30 3.60 A1 1.27 1.53
D4 11.84 12.39 A2 0.80 0.88
D5 11.84 12.39 A3 0.116 —
D6 5.91 6.46 A4 — 1.90
D7 10.65 11.20 φP — 6.60
D8 3.05 3.35 φb 0.43 0.50
E2 9.034 REF φb1 1.40 REF
E3 2.35 2.65 S 1.435 2.375
E4 7.25 7.80 L 3.05 3.31
E5 7.25 7.80 M 37
E6 8.86 9.41 N 453 (pins)
E7 8.86 9.41 e 1.27 BSC
E8 15.59 16.38 e1 2.54 BSC
Note:
1. Dimensions are given in millimeters.
Chapter 9 Mechanical Data 49
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Figure 13. AMD Duron™ Processor Model 7 CPGA Package
50 Mechanical Data Chapter 9
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Chapter 10 Pin Descriptions 51
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
10 Pin Descriptions
10.1 Pin Diagram and Pin Name Abbreviations
Figure 14 on page 52 shows the staggered Ceramic Pin Grid
Array (CPGA) for the AMD Duron™ processor model 7.
Because some of the pin names are too long to fit in the grid,
they are abbreviated. Figure 15 on page 53 shows the
bottomside view of the array. Table 19 on page 54 lists all the
pins in alphabetical order by pin name, along with the
abbreviation where necessary.
52 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A
SAO#12 SAO#5 SAO#3 SD#55 SD#61 SD#53 SD#63 SD#62 NC SD#57 SD#39 SD#35 SD#34 SD#44 NC SDOC#2 SD#40 SD#30
A
B
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
B
C
SAO#7 SAO#9 SAO#8 SAO#2 SD#54 SDOC#3 NC SD#51 SD#60 SD#59 SD#56 SD#37 SD#47 SD#38 SD#45 SD#43 SD#42 SD#41 SDOC#1
C
D
VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS
D
E
SAO#11 SAOC# SAO#4 SAO#6 SD#52 SD#50 SD#49 SDIC#3 SD#48 SD#58 SD#36 SD#46 NC SDIC#2 SD#33 SD#32 NC SD#31 SD#22
E
F
VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VCC VCC VCC
F
G
SAO#10 SAO#14 SAO#13 KEY KEY NC NC KEY KEY NC NC KEY KEY NC NC NC SD#20 SD#23 SD#21
G
H
VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS
H
J
SAO#0 SAO#1 NC VID[4] NC SD#19 SDIC#1 SD#29
J
K
VSS VSS VSS NC NC VCC VCC VCC
K
L
VID[0] VID[1] VID[2] VID[3] NC SD#26 NC SD#28
L
M
VCC VCC VCC VCC VSS VSS VSS VSS
M
N
PICCLK PICD#0 PICD#1 KEY NC SD#25 SD#27 SD#18
N
P
VSS VSS VSS VSS VCC VCC VCC VCC
P
Q
TCK TMS SCNSN KEY NC SD#24 SD#17 SD#16
Q
R
VCC VCC VCC VCC VSS VSS VSS VSS
R
S
SCNCK1 SCNINV SCNCK2 THDA NC SD#7 SD#15 SD#6
S
T
VSS VSS VSS VSS VCC VCC VCC VCC
T
U
TDI TRST# TDO THDC NC SD#5 SD#4 NC
U
V
VCC VCC VCC VCC VSS VSS VSS VSS
V
W
FID[0] FID[1] VREF_S NC NC SDIC#0 SD#2 SD#1
W
X
VSS VSS VSS VSS VCC VCC VCC VCC
X
Y
FID[2] FID[3] NC KEY NC NC SD#3 SD#12
Y
Z
VCC VCC VCC VCC VSS VSS VSS VSS
Z
AA
DBRDY DBREQ# NC KEY NC SD#8 SD#0 SD#13
AA
AB
VSS VSS VSS VSS VCC VCC VCC VCC
AB
AC
STPC# PLTST# ZN NC NC SD#10 SD#14 SD#11
AC
AD
VCC VCC VCC NC NC VSS VSS VSS
AD
AE
A20M# PWROK ZP NC NC SAI#5 SDOC#0 SD#9
AE
AF
VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC
AF
AG
FERR RESET# NC KEY KEY COREFB COREFB# KEY KEY NC NC NC NC KEY KEY NC SAI#2 SAI#11 SAI#7
AG
AH
VCC VCC AMD NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS
AH
AJ
IGNNE# INIT# VCC NC NC NC ANLOG NC NC NC CLKFR VCCA PLBYP# NC SAI#0 SFILLV# SAIC# SAI#6 SAI#3
AJ
AK
VSS VSS CPR# NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC
AK
AL
INTR FLUSH# VCC NC NC NC PLMN2 PLBYC# CLKIN# RCLK# K7CO CNNCT NC NC SAI#1 SDOV# SAI#8 SAI#4 SAI#10
AL
AM
VCC VSS VSS NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
AM
AN
NMI SMI# NC NC NC PLMN1 PLBYC CLKIN RCLK K7CO# PRCRDY NC NC SAI#12 SAI#14 SDINV# SAI#13 SAI#9
AN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
AMD Duron™ Processor
Model 7
Topside View
Figure 14. AMD Duron™ Processor Model 7 Pin Diagram—Topside View
Chapter 10 Pin Descriptions 53
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
A B C D E F G H J K L M N P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AJ AK AL AM AN
1
SAO#7 SAO#11 SAO#10 SAO#0 VID[0] PICCLK TCK SCNCK1 TDI FID[0] FID[2] DBRDY STPC# A20M# FERR IGNNE# INTR
1
2
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
2
3
SAO#12 SAO#9 SAOC# SAO#14 SAO#1 VID[1] PICD#0 TMS SCNINV TRST# FID[1] FID[3] DBREQ# PLTST# PWROK RESET# INIT# FLUSH# NMI
3
4
VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS
4
5
SAO#5 SAO#8 SAO#4 SAO#13 NC VID[2] PICD#1 SCNSN SCNCK2 TDO VREF_S NC NC ZN ZP NC VCC VCC SMI#
5
6
VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC AMD CPR# VSS
6
7
SAO#3 SAO#2 SAO#6 KEY VID[4] VID[3] KEY KEY THDA THDC NC KEY KEY NC NC KEY NC NC NC
7
8
VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC NC NC
8
9
SD#55 SD#54 SD#52 KEY KEYNCNCNC
9
10
VSS VSS VSS NC NC VCC VCC VCC
10
11
SD#61 SDOC#3 SD#50 NC COREFB NC NC NC
11
12
VCC VCC VCC VCC VSS VSS VSS VSS
12
13
SD#53 NC SD#49 NC COREFB# ANLOG PLMN2 PLMN1
13
14
VSS VSS VSS VSS VCC VCC VCC VCC
14
15
SD#63 SD#51 SDIC#3 KEY KEY NC PLBYC# PLBYC
15
16
VCC VCC VCC VCC VSS VSS VSS VSS
16
17
SD#62 SD#60 SD#48 KEY KEY NC CLKIN# CLKIN
17
18
VSS VSS VSS VSS VCC VCC VCC VCC
18
19
NC SD#59 SD#58 NC NC NC RCLK# RCLK
19
20
VCC VCC VCC VCC VSS VSS VSS VSS
20
21
SD#57 SD#56 SD#36 NC NC CLKFR K7CO K7CO#
21
22
VSS VSS VSS VSS VCC VCC VCC VCC
22
23
SD#39 SD#37 SD#46 KEY NC VCCA CNNCT PRCRDY
23
24
VCC VCC VCC VCC VSS VSS VSS VSS
24
25
SD#35 SD#47 NC KEY NC PLBYP# NC NC
25
26
VSS VSS VSS VSS VCC VCC VCC VCC
26
27
SD#34 SD#38 SDIC#2 NC KEYNCNCNC
27
28
VCC VCC VCC NC NC VSS VSS VSS
28
29
SD#44 SD#45 SD#33 NC KEY SAI#0 SAI#1 SAI#12
29
30
VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC
30
31
NC SD#43 SD#32 NC NC NC NC NC NC NC NC NC NC NC NC NC SFILLV# SDOV# SAI#14
31
32
VCC VCC VCC NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS
32
33
SDOC#2 SD#42 NC SD#20 SD#19 SD#26 SD#25 SD#24 SD#7 SD#5 SDIC#0 NC SD#8 SD#10 SAI#5 SAI#2 SAIC# SAI#8 SDINV#
33
34
VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC
34
35
SD#40 SD#41 SD#31 SD#23 SDIC#1 NC SD#27 SD#17 SD#15 SD#4 SD#2 SD#3 SD#0 SD#14 SDOC#0 SAI#11 SAI#6 SAI#4 SAI#13
35
36
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
36
37
SD#30 SDOC#1 SD#22 SD#21 SD#29 SD#28 SD#18 SD#16 SD#6 NC SD#1 SD#12 SD#13 SD#11 SD#9 SAI#7 SAI#3 SAI#10 SAI#9
37
A B C D E F G H J K L M N P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AJ AK AL AM AN
AMD Duron™ Processor
Model 7
Bottomside View
Figure 15. AMD Duron™ Processor Model 7 Pin Diagram—Bottomside View
54 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Table 19. Pin Name Abbreviations
Abbreviation Full Name Pin
A20M# AE1
AMD AH6
ANLOG ANALOG AJ13
CLKFR CLKFWDRST AJ21
CLKIN AN17
CLKIN# AL17
CNNCT CONNECT AL23
COREFB AG11
COREFB# AG13
CPR# CPU_PRESENCE# AK6
DBRDY AA1
DBREQ# AA3
FERR AG1
FID[0] W1
FID[1] W3
FID[2] Y1
FID[3] Y3
FLUSH# AL3
IGNNE# AJ1
INIT# AJ3
INTR AL1
K7CO K7CLKOUT AL21
K7CO# K7CLKOUT# AN21
KEY G7
KEY G9
KEY G15
KEY G17
KEY G23
KEY G25
KEY N7
KEY Q7
KEY Y7
KEY AA7
KEY AG7
KEY AG9
KEY AG15
KEY AG17
KEY AG27
KEY AG29
NC A19
NC A31
NC C13
NC E25
NC E33
NC F8
NC F30
NC G11
NC G13
NC G19
NC G21
NC G27
NC G29
NC G31
NC H6
NC H8
NC H10
NC H28
NC H30
NC H32
NC J5
NC J31
NC K8
NC K30
NC L31
NC L35
NC N31
NC Q31
NC S31
NC U31
NC U37
NC W7
NC W31
NC Y5
NC Y31
NC Y33
NC AA5
NC AA31
NC AC7
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
Chapter 10 Pin Descriptions 55
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
NC AC31
NC AD8
NC AD30
NC AE7
NC AE31
NC AF6
NC AF8
NC AF10
NC AF28
NC AF30
NC AF32
NC AG5
NC AG19
NC AG21
NC AG23
NC AG25
NC AG31
NC AH8
NC AH30
NC AJ7
NC AJ9
NC AJ11
NC AJ15
NC AJ17
NC AJ19
NC AJ27
NC AK8
NC AL7
NC AL9
NC AL11
NC AL25
NC AL27
NC AM8
NC AN7
NC AN9
NC AN11
NC AN25
NC AN27
NMI AN3
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
PICCLK N1
PICD#0 PICD[0]# N3
PICD#1 PICD[1]# N5
PLBYP# PLLBYPASS# AJ25
PLBYC PLLBYPASSCLK AN15
PLBYC# PLLBYPASSCLK# AL15
PLMN1 PLLMON1 AN13
PLMN2 PLLMON2 AL13
PLTST# PLLTEST# AC3
PRCRDY PROCREADY AN23
PWROK AE3
RESET# AG3
RCLK RSTCLK AN19
RCLK# RSTCLK# AL19
SAI#0 SADDIN[0]# AJ29
SAI#1 SADDIN[1]# AL29
SAI#2 SADDIN[2]# AG33
SAI#3 SADDIN[3]# AJ37
SAI#4 SADDIN[4]# AL35
SAI#5 SADDIN[5]# AE33
SAI#6 SADDIN[6]# AJ35
SAI#7 SADDIN[7]# AG37
SAI#8 SADDIN[8]# AL33
SAI#9 SADDIN[9]# AN37
SAI#10 SADDIN[10]# AL37
SAI#11 SADDIN[11]# AG35
SAI#12 SADDIN[12]# AN29
SAI#13 SADDIN[13]# AN35
SAI#14 SADDIN[14]# AN31
SAIC# SADDINCLK# AJ33
SAO#0 SADDOUT[0]# J1
SAO#1 SADDOUT[1]# J3
SAO#2 SADDOUT[2]# C7
SAO#3 SADDOUT[3]# A7
SAO#4 SADDOUT[4]# E5
SAO#5 SADDOUT[5]# A5
SAO#6 SADDOUT[6]# E7
SAO#7 SADDOUT[7]# C1
SAO#8 SADDOUT[8]# C5
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
56 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
SAO#9 SADDOUT[9]# C3
SAO#10 SADDOUT[10]# G1
SAO#11 SADDOUT[11]# E1
SAO#12 SADDOUT[12]# A3
SAO#13 SADDOUT[13]# G5
SAO#14 SADDOUT[14]# G3
SAOC# SADDOUTCLK# E3
SCNCK1 SCANCLK1 S1
SCNCK2 SCANCLK2 S5
SCNINV SCANINTEVAL S3
SCNSN SCANSHIFTEN Q5
SD#0 SDATA[0]# AA35
SD#1 SDATA[1]# W37
SD#2 SDATA[2]# W35
SD#3 SDATA[3]# Y35
SD#4 SDATA[4]# U35
SD#5 SDATA[5]# U33
SD#6 SDATA[6]# S37
SD#7 SDATA[7]# S33
SD#8 SDATA[8]# AA33
SD#9 SDATA[9]# AE37
SD#10 SDATA[10]# AC33
SD#11 SDATA[11]# AC37
SD#12 SDATA[12]# Y37
SD#13 SDATA[13]# AA37
SD#14 SDATA[14]# AC35
SD#15 SDATA[15]# S35
SD#16 SDATA[16]# Q37
SD#17 SDATA[17]# Q35
SD#18 SDATA[18]# N37
SD#19 SDATA[19]# J33
SD#20 SDATA[20]# G33
SD#21 SDATA[21]# G37
SD#22 SDATA[22]# E37
SD#23 SDATA[23]# G35
SD#24 SDATA[24]# Q33
SD#25 SDATA[25]# N33
SD#26 SDATA[26]# L33
SD#27 SDATA[27]# N35
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
SD#28 SDATA[28]# L37
SD#29 SDATA[29]# J37
SD#30 SDATA[30]# A37
SD#31 SDATA[31]# E35
SD#32 SDATA[32]# E31
SD#33 SDATA[33]# E29
SD#34 SDATA[34]# A27
SD#35 SDATA[35]# A25
SD#36 SDATA[36]# E21
SD#37 SDATA[37]# C23
SD#38 SDATA[38]# C27
SD#39 SDATA[39]# A23
SD#40 SDATA[40]# A35
SD#41 SDATA[41]# C35
SD#42 SDATA[42]# C33
SD#43 SDATA[43]# C31
SD#44 SDATA[44]# A29
SD#45 SDATA[45]# C29
SD#46 SDATA[46]# E23
SD#47 SDATA[47]# C25
SD#48 SDATA[48]# E17
SD#49 SDATA[49]# E13
SD#50 SDATA[50]# E11
SD#51 SDATA[51]# C15
SD#52 SDATA[52]# E9
SD#53 SDATA[53]# A13
SD#54 SDATA[54]# C9
SD#55 SDATA[55]# A9
SD#56 SDATA[56]# C21
SD#57 SDATA[57]# A21
SD#58 SDATA[58]# E19
SD#59 SDATA[59]# C19
SD#60 SDATA[60]# C17
SD#61 SDATA[61]# A11
SD#62 SDATA[62]# A17
SD#63 SDATA[63]# A15
SDIC#0 SDATAINCLK[0]# W33
SDIC#1 SDATAINCLK[1]# J35
SDIC#2 SDATAINCLK[2]# E27
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
Chapter 10 Pin Descriptions 57
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
SDIC#3 SDATAINCLK[3]# E15
SDINV# SDATAINVALID# AN33
SDOC#0 SDATAOUTCLK[0]# AE35
SDOC#1 SDATAOUTCLK[1]# C37
SDOC#2 SDATAOUTCLK[2]# A33
SDOC#3 SDATAOUTCLK[3]# C11
SDOV# SDATAOUTVALID# AL31
SFILLV# SFILLVALID# AJ31
SMI# AN5
STPC# STPCLK# AC1
TCK Q1
TDI U1
TDO U5
THDA THERMDA S7
THDC THERMDC U7
TMS Q3
TRST# U3
VCC VCC_CORE B4
VCC VCC_CORE B8
VCC VCC_CORE B12
VCC VCC_CORE B16
VCC VCC_CORE B20
VCC VCC_CORE B24
VCC VCC_CORE B28
VCC VCC_CORE B32
VCC VCC_CORE B36
VCC VCC_CORE D2
VCC VCC_CORE D4
VCC VCC_CORE D8
VCC VCC_CORE D12
VCC VCC_CORE D16
VCC VCC_CORE D20
VCC VCC_CORE D24
VCC VCC_CORE D28
VCC VCC_CORE D32
VCC VCC_CORE F12
VCC VCC_CORE F16
VCC VCC_CORE F20
VCC VCC_CORE F24
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VCC VCC_CORE F28
VCC VCC_CORE F32
VCC VCC_CORE F34
VCC VCC_CORE F36
VCC VCC_CORE H2
VCC VCC_CORE H4
VCC VCC_CORE H12
VCC VCC_CORE H16
VCC VCC_CORE H20
VCC VCC_CORE H24
VCC VCC_CORE K32
VCC VCC_CORE K34
VCC VCC_CORE K36
VCC VCC_CORE M2
VCC VCC_CORE M4
VCC VCC_CORE M6
VCC VCC_CORE M8
VCC VCC_CORE P30
VCC VCC_CORE P32
VCC VCC_CORE P34
VCC VCC_CORE P36
VCC VCC_CORE R2
VCC VCC_CORE R4
VCC VCC_CORE R6
VCC VCC_CORE R8
VCC VCC_CORE T30
VCC VCC_CORE T32
VCC VCC_CORE T34
VCC VCC_CORE T36
VCC VCC_CORE V2
VCC VCC_CORE V4
VCC VCC_CORE V6
VCC VCC_CORE V8
VCC VCC_CORE X30
VCC VCC_CORE X32
VCC VCC_CORE X34
VCC VCC_CORE X36
VCC VCC_CORE Z2
VCC VCC_CORE Z4
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
58 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
VCC VCC_CORE Z6
VCC VCC_CORE Z8
VCC VCC_CORE AB30
VCC VCC_CORE AB32
VCC VCC_CORE AB34
VCC VCC_CORE AB36
VCC VCC_CORE AD2
VCC VCC_CORE AD4
VCC VCC_CORE AD6
VCC VCC_CORE AF14
VCC VCC_CORE AF18
VCC VCC_CORE AF22
VCC VCC_CORE AF26
VCC VCC_CORE AF34
VCC VCC_CORE AF36
VCC VCC_CORE AH2
VCC VCC_CORE AH4
VCC VCC_CORE AH10
VCC VCC_CORE AH14
VCC VCC_CORE AH18
VCC VCC_CORE AH22
VCC VCC_CORE AH26
VCC VCC_CORE AK10
VCC VCC_CORE AK14
VCC VCC_CORE AK18
VCC VCC_CORE AK22
VCC VCC_CORE AK26
VCC VCC_CORE AK30
VCC VCC_CORE AK34
VCC VCC_CORE AK36
VCC VCC_CORE AJ5
VCC VCC_CORE AL5
VCC VCC_CORE AM2
VCC VCC_CORE AM10
VCC VCC_CORE AM14
VCC VCC_CORE AM18
VCC VCC_CORE AM22
VCC VCC_CORE AM26
VCC VCC_CORE AM22
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VCC VCC_CORE AM26
VCC VCC_CORE AM30
VCC VCC_CORE AM34
VCCA AJ23
VID[0] L1
VID[1] L3
VID[2] L5
VID[3] L7
VID[4] J7
VREF_S VREF_SYS W5
VSS B2
VSS B6
VSS B10
VSS B14
VSS B18
VSS B22
VSS B26
VSS B30
VSS B34
VSS D6
VSS D10
VSS D14
VSS D18
VSS D22
VSS D26
VSS D30
VSS D34
VSS D36
VSS F2
VSS F4
VSS F6
VSS F10
VSS F14
VSS F18
VSS F22
VSS F26
VSS H14
VSS H18
VSS H22
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
Chapter 10 Pin Descriptions 59
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
VSS H26
VSS H34
VSS H36
VSS K2
VSS K4
VSS K6
VSS M30
VSS M32
VSS M34
VSS M36
VSS P2
VSS P4
VSS P6
VSS P8
VSS R30
VSS R32
VSS R34
VSS R36
VSS T2
VSS T4
VSS T6
VSS T8
VSS V30
VSS V32
VSS V34
VSS V36
VSS X2
VSS X4
VSS X6
VSS X8
VSS Z30
VSS Z32
VSS Z34
VSS Z36
VSS AB2
VSS AB8
VSS AB4
VSS AB6
VSS AD32
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
VSS AD34
VSS AD36
VSS AF2
VSS AF4
VSS AF12
VSS AF16
VSS AH12
VSS AH16
VSS AH20
VSS AH24
VSS AH28
VSS AH32
VSS AH34
VSS AH36
VSS AK2
VSS AK4
VSS AK12
VSS AK16
VSS AK20
VSS AK24
VSS AK28
VSS AK32
VSS AM4
VSS AM6
VSS AM12
VSS AM16
VSS AM20
VSS AM24
VSS AM28
VSS AM32
VSS AM36
ZN AC5
ZP AE5
Table 19. Pin Name Abbreviations (continued)
Abbreviation Full Name Pin
60 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
A1 No Pin page 72 - - -
A3 SADDOUT[12]# P O G
A5 SADDOUT[5]# P O G
A7 SADDOUT[3]# P O G
A9 SDATA[55]# P B P
A11 SDATA[61]# P B P
A13 SDATA[53]# P B G
A15 SDATA[63]# P B G
A17 SDATA[62]# P B G
A19 NC Pin page 72 - - -
A21 SDATA[57]# P B G
A23 SDATA[39]# P B G
A25 SDATA[35]# P B P
A27 SDATA[34]# P B P
A29 SDATA[44]# P B G
A31 NC Pin page 72 - - -
A33 SDATAOUTCLK[2]# P O P
A35 SDATA[40]# P B G
A37 SDATA[30]# P B P
B2 VSS ---
B4 VCC_CORE ---
B6 VSS ---
B8 VCC_CORE ---
B10 VSS ---
B12 VCC_CORE ---
B14 VSS ---
B16 VCC_CORE ---
B18 VSS ---
B20 VCC_CORE ---
B22 VSS ---
B24 VCC_CORE ---
B26 VSS ---
B28 VCC_CORE ---
B30 VSS ---
B32 VCC_CORE ---
B34 VSS ---
B36 VCC_CORE ---
C1 SADDOUT[7]# P O G
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
10.2 Pin List
Table 20 cross-references Socket A pin location to signal name.
The “L” (Level) column shows the electrical specification for
this pin. “P” indicates a push-pull mode driven by a single
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: The AMD Duron processor supports push-pull drivers. For
more information, see “Push-Pull (PP) Drivers” on page 6.
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or VCC_CORE (P) planes for the purpose of signal routing with
respect to the current return paths.
Chapter 10 Pin Descriptions 61
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
C3 SADDOUT[9]# P O G
C5 SADDOUT[8]# P O G
C7 SADDOUT[2]# P O G
C9 SDATA[54]# P B P
C11 SDATAOUTCLK[3]# P O G
C13 NC Pin page 72 - - -
C15 SDATA[51]# P B P
C17 SDATA[60]# P B G
C19 SDATA[59]# P B G
C21 SDATA[56]# P B G
C23 SDATA[37]# P B P
C25 SDATA[47]# P B G
C27 SDATA[38]# P B G
C29 SDATA[45]# P B G
C31 SDATA[43]# P B G
C33 SDATA[42]# P B G
C35 SDATA[41]# P B G
C37 SDATAOUTCLK[1]# P O G
D2 VCC_CORE ---
D4 VCC_CORE ---
D6 VSS ---
D8 VCC_CORE ---
D10 VSS ---
D12 VCC_CORE ---
D14 VSS ---
D16 VCC_CORE ---
D18 VSS ---
D20VCC_CORE ---
D22VSS ---
D24VCC_CORE ---
D26VSS ---
D28VCC_CORE ---
D30VSS ---
D32VCC_CORE ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
D34VSS ---
D36VSS ---
E1 SADDOUT[11]# P O P
E3 SADDOUTCLK# P O G
E5 SADDOUT[4]# P O P
E7 SADDOUT[6]# P O G
E9 SDATA[52]# P B P
E11 SDATA[50]# P B P
E13 SDATA[49]# P B G
E15 SDATAINCLK[3]# P I G
E17 SDATA[48]# P B P
E19 SDATA[58]# P B G
E21 SDATA[36]# P B P
E23 SDATA[46]# P B P
E25 NC Pin page 72 - - -
E27 SDATAINCLK[2]# P I G
E29 SDATA[33]# P B P
E31 SDATA[32]# P B P
E33 NC Pin page 72 - - -
E35 SDATA[31]# P B P
E37 SDATA[22]# P B G
F2 VSS ---
F4 VSS ---
F6 VSS ---
F8 NC Pin page 72 - - -
F10 VSS ---
F12 VCC_CORE ---
F14 VSS ---
F16 VCC_CORE ---
F18 VSS ---
F20 VCC_CORE ---
F22 VSS ---
F24 VCC_CORE ---
F26 VSS ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
62 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
F28 VCC_CORE ---
F30 NC Pin page 72 - - -
F32 VCC_CORE ---
F34 VCC_CORE ---
F36 VCC_CORE ---
G1 SADDOUT[10]# P O P
G3 SADDOUT[14]# P O G
G5 SADDOUT[13]# P O G
G7 Key Pin page 71 - - -
G9 Key Pin page 71 - - -
G11 NC Pin page 72 - - -
G13 NC Pin page 72 - - -
G15 Key Pin page 71 - - -
G17 Key Pin page 71 - - -
G19 NC Pin page 72 - - -
G21 NC Pin page 72 - - -
G23 Key Pin page 71 - - -
G25 Key Pin page 71 - - -
G27 NC Pin page 72 - - -
G29 NC Pin page 72 - - -
G31 NC Pin page 72 - - -
G33 SDATA[20]# P B G
G35 SDATA[23]# P B G
G37 SDATA[21]# P B G
H2 VCC_CORE ---
H4 VCC_CORE ---
H6 NC Pin page 72 - - -
H8 NC Pin page 72 - - -
H10 NC Pin page 72 - - -
H12 VCC_CORE ---
H14 VSS ---
H16 VCC_CORE ---
H18 VSS ---
H20VCC_CORE ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
H22VSS ---
H24VCC_CORE ---
H26VSS ---
H28 NC Pin page 72 - - -
H30 NC Pin page 72 - - -
H32 NC Pin page 72 - - -
H34VSS ---
H36VSS ---
J1 SADDOUT[0]# page 72 P O -
J3 SADDOUT[1]# page 72 P O -
J5 NC Pin page 72 - - -
J7 VID[4] page 73 O O -
J31 NC Pin page 72 - - -
J33 SDATA[19]# P B G
J35 SDATAINCLK[1]# P I P
J37 SDATA[29]# P B P
K2 VSS ---
K4 VSS ---
K6 VSS ---
K8 NC Pin page 72 - - -
K30 NC Pin page 72 - - -
K32VCC_CORE ---
K34VCC_CORE ---
K36VCC_CORE ---
L1 VID[0] page 73 O O -
L3 VID[1] page 73 O O -
L5 VID[2] page 73 O O -
L7 VID[3] page 73 O O -
L31 NC Pin page 72 - - -
L33 SDATA[26]# P B P
L35 NC Pin page 72 - - -
L37 SDATA[28]# P B P
M2 VCC_CORE ---
M4 VCC_CORE ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
Chapter 10 Pin Descriptions 63
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
M6 VCC_CORE ---
M8 VCC_CORE ---
M30VSS ---
M32VSS ---
M34VSS ---
M36VSS ---
N1 PICCLK page 68 O I -
N3 PICD#[0] page 68 O B -
N5 PICD#[1] page 68 O B -
N7 Key Pin page 71 - - -
N31 NC Pin page 72 - - -
N33 SDATA[25]# P B P
N35 SDATA[27]# P B P
N37 SDATA[18]# P B G
P2 VSS ---
P4 VSS ---
P6 VSS ---
P8 VSS ---
P30 VCC_CORE ---
P32 VCC_CORE ---
P34 VCC_CORE ---
P36 VCC_CORE ---
Q1 TCK page 71 P I -
Q3 TMS page 71 P I -
Q5 SCANSHIFTEN page 72 P I -
Q7 Key Pin page 71 - - -
Q31 NC Pin page 72 - - -
Q33 SDATA[24]# P B P
Q35 SDATA[17]# P B G
Q37 SDATA[16]# P B G
R2 VCC_CORE - - -
R4 VCC_CORE - - -
R6 VCC_CORE - - -
R8 VCC_CORE - - -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
R30 VSS ---
R32 VSS ---
R34 VSS ---
R36 VSS ---
S1 SCANCLK1 page 72 P I -
S3 SCANINTEVAL page 72 P I -
S5 SCANCLK2 page 72 P I -
S7 THERMDA page 73 - - -
S31 NC Pin page 72 - - -
S33 SDATA[7]# P B G
S35 SDATA[15]# P B P
S37 SDATA[6]# P B G
T2 VSS ---
T4 VSS ---
T6 VSS ---
T8 VSS ---
T30 VCC_CORE ---
T32 VCC_CORE ---
T34 VCC_CORE ---
T36 VCC_CORE ---
U1 TDI page 71 P I -
U3 TRST# page 71 P I -
U5 TDO page 71 P O -
U7 THERMDC page 73 - - -
U31 NC Pin page 72 - - -
U33 SDATA[5]# P B G
U35 SDATA[4]# P B G
U37 NC Pin page 72 - - -
V2 VCC_CORE - - -
V4 VCC_CORE - - -
V6 VCC_CORE - - -
V8 VCC_CORE - - -
V30 VSS ---
V32 VSS ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
64 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
V34 VSS ---
V36 VSS ---
W1 FID[0] page 70 O O -
W3 FID[1] page 70 O O -
W5 VREFSYS page 74 P - -
W7 NC Pin page 72 - - -
W31 NC Pin page 72 - - -
W33 SDATAINCLK[0]# P I G
W35 SDATA[2]# P B G
W37 SDATA[1]# P B P
X2 VSS ---
X4 VSS ---
X6 VSS ---
X8 VSS ---
X30 VCC_CORE ---
X32 VCC_CORE ---
X34 VCC_CORE ---
X36 VCC_CORE ---
Y1 FID[2] page 70 O O -
Y3 FID[3] page 70 O O -
Y5 NC Pin page 72 - - -
Y7 Key Pin page 71 - - -
Y31 NC Pin page 72 - - -
Y33 NC Pin page 72 - - -
Y35 SDATA[3]# P B G
Y37 SDATA[12]# P B P
Z2 VCC_CORE ---
Z4 VCC_CORE ---
Z6 VCC_CORE ---
Z8 VCC_CORE ---
Z30 VSS ---
Z32 VSS ---
Z34 VSS ---
Z36 VSS ---
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
AA1 DBRDY page 69 P O -
AA3 DBREQ# page 69 P I -
AA5NC ---
AA7 Key Pin page 71 - - -
AA31 NC Pin page 72 - - -
AA33 SDATA[8]# P B P
AA35 SDATA[0]# P B G
AA37 SDATA[13]# P B G
AB2VSS ---
AB4VSS ---
AB6VSS ---
AB8VSS ---
AB30 VCC_CORE - - -
AB32 VCC_CORE - - -
AB34 VCC_CORE - - -
AB36 VCC_CORE - - -
AC1 STPCLK# page 73 P I -
AC3 PLLTEST# page 72 P I -
AC5 ZN page 74 P - -
AC7NC ---
AC31 NC Pin page 72 - - -
AC33 SDATA[10]# P B P
AC35 SDATA[14]# P B G
AC37 SDATA[11]# P B G
AD2VCC_CORE ---
AD4VCC_CORE ---
AD6VCC_CORE ---
AD8 NC Pin page 72 - - -
AD30 NC Pin page 72 - - -
AD32VSS ---
AD34VSS ---
AD36VSS ---
AE1 A20M# P I -
AE3 PWROK P I -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
Chapter 10 Pin Descriptions 65
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
AE5 ZP page 74 P - -
AE7 NC ---
AE31 NC Pin page 72 - - -
AE33 SADDIN[5]# P I G
AE35 SDATAOUTCLK[0]# P O P
AE37 SDATA[9]# P B G
AF2 VSS ---
AF4 VSS ---
AF6 NC Pin page 72 - - -
AF8 NC Pin page 72 - - -
AF10 NC Pin page 72 - - -
AF12VSS ---
AF14 VCC_CORE - - -
AF16VSS ---
AF18 VCC_CORE - - -
AF20VSS ---
AF22 VCC_CORE - - -
AF24VSS ---
AF26 VCC_CORE - - -
AF28 NC Pin page 72 - - -
AF30 NC Pin page 72 - - -
AF32 NC Pin page 72 - - -
AF34 VCC_CORE - - -
AF36 VCC_CORE - - -
AG1 FERR page 69 P O -
AG3 RESET# - I -
AG5 NC Pin page 72 - - -
AG7 Key Pin page 71 - - -
AG9 Key Pin page 71 - - -
AG11 COREFB page 69 - - -
AG13 COREFB# page 69 - - -
AG15 Key Pin page 71 - - -
AG17 Key Pin page 71 - - -
AG19 NC Pin page 72 - - -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
AG21 NC Pin page 72 - - -
AG23 NC Pin page 72 - - -
AG25 NC Pin page 72 - - -
AG27 Key Pin page 71 - - -
AG29 Key Pin page 71 - - -
AG31 NC Pin page 72 - - -
AG33 SADDIN[2]# P I G
AG35 SADDIN[11]# P I G
AG37 SADDIN[7]# P I P
AH2VCC_CORE ---
AH4VCC_CORE ---
AH6 AMD Pin page 68 - - -
AH8 NC Pin page 72 - - -
AH10 VCC_CORE - - -
AH12VSS ---
AH14 VCC_CORE - - -
AH16VSS ---
AH18 VCC_CORE - - -
AH20VSS ---
AH22 VCC_CORE - - -
AH24VSS ---
AH26 VCC_CORE - - -
AH28VSS ---
AH30 NC Pin page 72 - - -
AH32VSS ---
AH34VSS ---
AH36VSS ---
AJ1 IGNNE# page 71 P I -
AJ3 INIT# page 71 P I -
AJ5 VCC_CORE ---
AJ7 NC Pin page 72 - - -
AJ9 NC Pin page 72 - - -
AJ11 NC Pin page 72 - - -
AJ13 Analog page 68 - - -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
66 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
AJ15 NC Pin page 72 - - -
AJ17 NC Pin page 72 - - -
AJ19 NC Pin page 72 - - -
AJ21 CLKFWDRST page 68 P I P
AJ23 VCCA page 73 - - -
AJ25 PLLBYPASS# page 72 P I -
AJ27 NC Pin page 72 - - -
AJ29 SADDIN[0]# page 72 P I -
AJ31 SFILLVALID# P I G
AJ33 SADDINCLK# P I G
AJ35 SADDIN[6]# P I P
AJ37 SADDIN[3]# P I G
AK2 VSS - - -
AK4 VSS - - -
AK6 CPU_PRESENCE# page 69 - - -
AK8 NC Pin page 72 - - -
AK10 VCC_CORE - - -
AK12 VSS - - -
AK14 VCC_CORE - - -
AK16 VSS - - -
AK18 VCC_CORE - - -
AK20 VSS - - -
AK22 VCC_CORE - - -
AK24 VSS - - -
AK26 VCC_CORE - - -
AK28 VSS - - -
AK30 VCC_CORE - - -
AK32 VSS - - -
AK34 VCC_CORE - - -
AK36 VCC_CORE - - -
AL1 INTR page 71 P I -
AL3 FLUSH# page 71 P I -
AL5 VCC_CORE ---
AL7 NC Pin page 72 - - -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
AL9 NC Pin page 72 - - -
AL11 NC Pin page 72 - - -
AL13 PLLMON2 page 72 O O -
AL15 PLLBYPASSCLK# page 72 P I -
AL17 CLKIN# page 68 P I P
AL19 RSTCLK# page 68 P I P
AL21 K7CLKOUT page 71 P O -
AL23 CONNECT page 69 P I P
AL25 NC Pin page 72 - - -
AL27 NC Pin page 72 - - -
AL29 SADDIN[1]# page 72 P I -
AL31 SDATAOUTVALID# P O P
AL33 SADDIN[8]# P I P
AL35 SADDIN[4]# P I G
AL37 SADDIN[10]# P I G
AM2VCC_CORE ---
AM4VSS ---
AM6VSS ---
AM8 NC Pin page 72 - - -
AM10 VCC_CORE - - -
AM12VSS ---
AM14 VCC_CORE - - -
AM16VSS ---
AM18 VCC_CORE - - -
AM20VSS ---
AM22 VCC_CORE - - -
AM24VSS ---
AM26 VCC_CORE - - -
AM28VSS ---
AM30 VCC_CORE - - -
AM32VSS ---
AM34 VCC_CORE - - -
AM36VSS ---
AN1 No Pin page 72 - - -
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
Chapter 10 Pin Descriptions 67
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
AN3 NMI P I -
AN5 SMI# P I -
AN7 NC Pin page 72 - - -
AN9 NC Pin page 72 - - -
AN11 NC Pin page 72 - - -
AN13 PLLMON1 page 72 O B -
AN15 PLLBYPASSCLK page 72 P I -
AN17 CLKIN page 68 P I P
AN19 RSTCLK page 68 P I P
AN21 K7CLKOUT# page 71 P O -
AN23 PROCRDY P O P
AN25 NC Pin page 72 - - -
AN27 NC Pin page 72 - - -
AN29 SADDIN[12]# P I G
AN31 SADDIN[14]# P I G
AN33 SDATAINVALID# P I P
AN35 SADDIN[13]# P I G
AN37 SADDIN[9]# P I G
Table 20. Cross-Reference by Pin Location
Pin Name Description L P R
(continued)
68 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
10.3 Detailed Pin Descriptions
The information in this section pertains to Table 20 on page 60.
A20M# Pin A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Pin AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Duron™ System
Bus Pins
See the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902 for information about the system
bus pins—PROCRDY, PWROK, RESET#, SADDIN[14:2]#,
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#,
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Pin Treat this pin as a NC.
APIC Pins, PICCLK,
PICD[1:0]#
The Advanced Programmable Interrupt Controller (APIC) is a
feature that provides a flexible and expandable means of
delivering interrupts in a system using an AMD processor. The
pins, PICD[1:0], are the bi-directional message-passing signals
used for the APIC and are driven to the Southbridge or a
dedicated I/O APIC. The pin, PICCLK, must be driven with a
valid clock input.
For more information, see Table 16, “APIC Pin AC and DC
Characteristics,” on page 41.
CLKFWDRST Pin CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CLKIN, RSTCLK
(SYSCLK) Pins
Connect CLKIN with RSTCLK and name it SYSCLK. Connect
CLKIN# with RSTCLK# and name it SYSCLK#. Length match
the clocks from the clock generator to the Northbridge and
processor.
Chapter 10 Pin Descriptions 69
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
See “SYSCLK and SYSCLK#” on page 73 for more information.
CONNECT Pin CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin CPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor in
the Socket A-style socket.
DBRDY and DBREQ#
Pins
DBRDY and DBREQ# are routed to the debug connector.
DBREQ# is tied to VCC_CORE with a pullup resistor.
FERR Pin FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
70 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 21 describes the encodings of the clock multipliers on
FID[3:0].
The FID[3:0] signals are open drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (Serialization Initialization Packet) that is
sent to the processor. The FID[3:0] signals are valid after
PWROK is asserted. The FID[3:0]signals must not be sampled
until they become valid. See the AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for more
information about Serialization Initialization Packets and SIP
protocol.
The processor FID[3:0] outputs are open drain and 2.5 V
tolerant. To prevent damage to the processor, if these signals
are pulled High to above 2.5 V, they must be electrically
Table 21. FID[3:0] Clock Multiplier Encodings
FID[3] FID[2] FID[1] FID[0]
Processor Clock to
SYSCLK Frequency
Ratio
0000 11
0001 11.5
0010 12
0011 ≥ 12.5*
0100 5
0101 5.5
0110 6
0111 6.5
1000 7
1001 7.5
1010 8
1011 8.5
1100 9
1101 9.5
1110 10
1111 10.5
Note:
*All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
Chapter 10 Pin Descriptions 71
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
isolated from the processor. For information about the FID[3:0]
isolation circuit, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
See “Frequency Identification (FID[3:0])” on page 27 for the
DC characteristics for FID[3:0].
FLUSH# Pin FLUSH# must be tied to VCC_CORE with a pullup resistor. If a
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# Pin IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# Pin INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
INTR Pin INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
JTAG Pins TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
Connect these pins directly to the motherboard debug
connector. Pull TDI, TCK, TMS, and TRST# up to VCC_CORE
with pullup resistors.
K7CLKOUT and
K7CLKOUT# Pins
K7CLKOUT and K7CLKOUT# are each run for two to three
inches and then terminated with a resistor pair: 100 ohms to
VCC_CORE and 100 ohms to VSS. The effective termination
resistance and voltage are 50 ohms and VCC_CORE/2.
Key Pins These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
See “NC Pins“ for more information.
72 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
NC Pins The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
resistors.
PWROK Pin The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 8, “Signal and Power-Up
Requirements” on page 43.
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The AMD Duron processor model 7 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
see the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902.
Scan Pins SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2
are the scan interface. This interface is AMD internal and is
tied disabled with pulldown resistors to ground on the
motherboard.
SMI# Pin SMI# is an input that causes the processor to enter the system
management mode.
Chapter 10 Pin Descriptions 73
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
STPCLK# Pin STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK# SYSCLK and SYSCLK# are differential input clock signals
provided to the PLL of the processor from a system-clock
generator.
See “CLKIN, RSTCLK (SYSCLK) Pins” on page 68 for more
information.
THERMDA and
THERMDC Pins
Thermal Diode anode and cathode pins are used to monitor the
actual temperature of the processor die, providing more
accurate temperature control to the system.
See Table 14, “Thermal Diode Electrical Characteristics,” on
page 39 for more information.
VCCA Pin VCCA is the processor PLL supply. For information about the
VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on
page 35 and the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
VID[4:0] Pins The VID[4:0] (Voltage Identification) outputs are used to
dictate the VCC_CORE voltage level. The VID[4:0] pins are
strapped to ground or left unconnected on the processor
package. The VID[4:0] pins are pulled-up on the motherboard
and used by the VCC_CORE DC/DC converter.
For more information, see Table 22, “VID[4:0] Code to Voltage
Definition,” on page 74.
74 Pin Descriptions Chapter 10
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
For more information, see the “Required Circuits” chapter of
the AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363.
VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus
input receivers. The value of VREFSYS is system specific. In
addition, to minimize VCC_CORE noise rejection from
VREFSYS, include decoupling capacitors. For more
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
ZN and ZP Pins ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to VCC_CORE with a resistor
that has a resistance matching the impedance Z0 of the
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z0 of the transmission line.
Table 22. VID[4:0] Code to Voltage Definition
VID[4:0] VCC_CORE (V) VID[4:0] VCC_CORE (V)
00000 1.850 10000 1.450
00001 1.825 10001 1.425
00010 1.800 10010 1.400
00011 1.775 10011 1.375
00100 1.750 10100 1.350
00101 1.725 10101 1.325
00111 1.675 10111 1.275
01000 1.650 11000 1.250
01001 1.625 11001 1.225
01010 1.600 11010 1.200
01011 1.575 11011 1.175
01100 1.550 11100 1.150
01101 1.525 11101 1.125
01110 1.500 11110 1.100
01111 1.475 11111 No CPU
Chapter 11 Ordering Information 75
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
11 Ordering Information
Standard AMD Duron™ Processor Model 7 Products
AMD standard products are available in several operating ranges. The ordering part
numbers (OPN) are formed by a combination of the elements, as shown in Figure 16.
Figure 16. OPN Example for the AMD Duron™ Processor Model 7
D1300 A M T 1 B
Note: Spaces are added to the number shown
above for viewing clarity only.
OPN
Max FSB: B = 200 MHz
Size of L2 Cache: 1 = 64 Kbytes
Die Temperature: T = 90ºC
Operating Voltage: M = 1.75V
Package Type: A = CPGA
Speed: 900 = 900 MHz, 950 = 950 MHz, 1000 =1000 MHz,
1100 =1100 MHz, 1200 = 1200 MHz, 1300 = 1300 MHz
Generation: HD = High-Performance Desktop Processor
Family/Architecture: D = AMD Duron™ Processor Model 7 Architecture
HD
76 Ordering Information Chapter 11
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Appendix A 77
Appendix A
Conventions and
Abbreviations
This section contains information about the conventions and
abbreviations used in this document.
Signals and Bits
■Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
■Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
78 Appendix A
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Invalid and Don’t-Care—In timing diagrams, signal ranges that
are invalid or don't-care are filled with a screen pattern.
Data Terminology
The following list defines data terminology:
■Quantities
•A word is two bytes (16 bits)
•A doubleword is four bytes (32 bits)
•A quadword is eight bytes (64 bits)
■Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
■Abbreviations—The following notation is used for bits and
bytes:
•Kilo (K, as in 4-Kbyte page)
•Mega (M, as in 4 Mbits/sec)
•Giga (G, as in 4 Gbytes of memory space)
■Little-Endian Convention—The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left—the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
■Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
■Bit Values—Bits can either be set to 1 or cleared to 0.
Hexadecimal and Binary Numbers—Unless the context makes
interpretation clear, hexadecimal numbers are followed by an h
and binary numbers are followed by a b.
See Table 23 on page 79 for more abbreviations.
Appendix A 79
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
Abbreviations and Acronyms
Table 23 contains the definitions of abbreviations used in this
document.
Table 23. Abbreviations
Abbreviation Meaning
AAmpere
F Farad
G Giga-
Gbit Gigabit
Gbyte Gigabyte
GHz Gigahertz
HHenry
h Hexadecimal
K Kilo-
Kbyte Kilobyte
lbf Foot-pound
M Mega-
Mbit Megabit
Mbyte Megabyte
MHz Megahertz
m Milli-
ms Millisecond
mW Milliwatt
µMicro-
µA Microampere
µF Microfarad
µH Microhenry
µs Microsecond
µV Microvolt
n nano-
nA nanoampere
nF nanofarad
nH nanohenry
ns nanosecond
ohm Ohm
80 Appendix A
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
Table 24 contains the definitions of acronyms used in this
document.
ppico-
pA picoampere
pF picofarad
pH picohenry
ps picosecond
s Second
VVolt
WWatt
Table 24. Acronyms
Abbreviation Meaning
ACPI Advanced Configuration and Power Interface
AGP Accelerated Graphics Port
APCI AGP Peripheral Component Interconnect
API Application Programming Interface
APIC Advanced Programmable Interrupt Controller
BIOS Basic Input/Output System
BIST Built-In Self-Test
BIU Bus Interface Unit
CPGA Ceramic Pin Grid Array
DDR Double-Data Rate
DIMM Dual Inline Memory Module
DMA Direct Memory Access
DRAM Direct Random Access Memory
EIDE Enhanced Integrated Device Electronics
EISA Extended Industry Standard Architecture
EPROM Enhanced Programmable Read Only Memory
FIFO First In, First Out
GART Graphics Address Remapping Table
HSTL High-Speed Transistor Logic
IDE Integrated Device Electronics
ISA Industry Standard Architecture
Table 23. Abbreviations (continued)
Abbreviation Meaning
Appendix A 81
24310G—January 2002 AMD Duron™ Processor Model 7 Data Sheet
Preliminary Information
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
LAN Large Area Network
LRU Least-Recently Used
LVTTL Low Voltage Transistor Transistor Logic
MSB Most Significant Bit
MTRR Memory Type and Range Registers
MUX Multiplexer
NMI Non-Maskable Interrupt
OD Open-Drain
OPGA Organic Pin Grid Array
PBGA Plastic Ball Grid Array
PA Physical Address
PCI Peripheral Component Interconnect
PDE Page Directory Entry
PDT Page Directory Table
PGA Pin Grid Array
PLL Phase Locked Loop
PMSM Power Management State Machine
POS Power-On Suspend
POST Power-On Self-Test
RAM Random Access Memory
ROM Read Only Memory
RXA Read Acknowledge Queue
SCSI Small Computer System Interface
SDI System DRAM Interface
SDRAM Synchronous Direct Random Access Memory
SIMD Single Instruction Multiple Data
SIP Serial Initialization Packet
SMbus System Management Bus
SPD Serial Presence Detect
SRAM Synchronous Random Access Memory
SROM Serial Read Only Memory
TLB Translation Lookaside Buffer
Table 24. Acronyms (continued)
Abbreviation Meaning
82 Appendix A
AMD Duron™ Processor Model 7 Data Sheet 24310G—January 2002
Preliminary Information
TOM Top of Memory
TTL Transistor Transistor Logic
VAS Virtual Address Space
VPA Virtual Page Address
VGA Video Graphics Adapter
USB Universal Serial Bus
ZDB Zero Delay Buffer
Table 24. Acronyms (continued)
Abbreviation Meaning
