Ordering number : EN4900A LC89971, 89971M Multi-system CCD Delay Line Overview The LC89971 and LC89971M are CCD delay lines for multi television systems. They incorporate a comb filter for chrominance signal and a 1H delay line for luminance signal. Structure - NMOS + CCD Functions * Two CCD shift registers (for chrominance and luminance signals) CCD drive circuits * CCD stage count switching circuit * CCD signal adder * Auto-bias circuit * Sync tip clamping circuit (luminance signal) * Center-bias circuit (chrominance signal) * Sample-and-hold circuit * PLL 4 x frequency multiplier * fsc clock output circuit * RD voltage generator Features * 5 V single-voltage power supply * Built-in PLL 4 x frequency multiplier circuit allows 4 fsc operation from an fsc (3.58 MHz) input. * Control pin switchable to handle NTSC/M, PAL/GBI and PAL/M systems. Package Dimensions unit: mm 3059-DIP22S {Lcss971] naenaneannt 7 - i FuUuUuNUDUOO m2 g th, 1 3 ms othe SANYO: DIP22S unit: mm 3045B-MFP24 [LC89971M) 4 REAR ARAARRRAR * Built-in chrominance signal crosstalk exclusion comb be es filter features high precision comb characteristics in an He | | adjustment-free circuit. iHHRBRBRBEB BEB ae * Built-in peripheral circuits allow applications to be 18-3 da eel constructed with a minimum number of external Hr : 1 components. tt Td we : . ae : 0.35 La > Positive-phase signal input/positive-phase signal output (luminance signal) ge . SANYO: MFP24 Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Ratings Unit Maximum supply voltage Vop max ~0.3 to +6.0 Vv L.Gag971 1200 mW cats ani Allowable power dissipation Pd max LCBOS7IM 500 a Operating temperature Topr -10 to +70 c Storage temperature Tstg +55 16 +150 C SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63095 TH (OT) No. 4900-19LC89971, 89971M Allowable Operating Ranges at Ta = 25C Parameter Symbol Conditions min typ max Unit Supply voltage Voo 4.75 5.00 .25 Vv Glock input amplitude Veik 300 500 1000 mVp-p Clock frequency Feik Sine wave _ 3.579545 _ MHz Clock signal input amplitude Vin-c _ 350 500 mVp-p Luminance signal input amplitude Viney _- 400 $72 mYVp-p Electrical Characteristics at Vop = 5.0 V,Ta= 25C, Fcik = 3.579545 MHz, VeLK = 500 mp-p Parameter Switch states Symbol ye" Tew sw2 SW3 sw4 Conditions min typ max Unit Supply currant Ipp.1 a a Ipo-2 a b lpo-a b b pp or 45 55 65 mA Chrominance System Characterist ies (with no Y-IN input) Pin voltage (input) VINC+1 a Vinc-2 Vinc-3 Pin voltage (output) Voure-1 Voute-2 Voute-a 2.0 24 28 Vv 1.6 2.0 v Voltage gain Gyo. Gyc.g Gyo.3 -2 Comb depth Co. Co.2 Co.5 | -~40 35 dB Linearity Lye Lwe-2 Lwe-a 0.0 +03 dB Clock leakage (4 fsc} Lekac.s Lexac-2 Loxac-a Clock leakage (fsc} Lokic-1 Lexic-2 Lekic-3 mrms 6.8 15 mVrms Noise No.1 No.2 eT Po Pe st el ciocgiel |e | opel ol ei elope re ele el ol all No.3 oc 0.5 2.0 mVims Output impedance 200-1 a,b Zoc-2 a,b Zoc-3 a,b 200 350 00 n 0H delay time Toc. Toc-2 FIelel~olal wlole;walopwe ie ole ie lola l/ ea foley e royale lola iol ole Tpe-3 Syoloel/ofolol/o[oljei olrlio pole lip iol oj a iofpe |e ifopope Poy ete pol el PLO se ois; se ole wyiale lol wl ae elope (el a ea ole ie) mle ee] ep] 230 - ns Continued on next page. No. 4900-2/9LC89971, 89971M Continued from preceding page. Parameter Symbot! Switch states swi | sw2 | sw3 | swe Conditions min typ max Unit Luminance System Characteristics (with no C-IN1 or C-IN2 input) Pin voltage (input) Viny-1 p Viny2 Viny-3 Pin voliage (output) Vouty-1 Vourty-2 VourTyY-3 17 2.1 2.5 0.8 Voltage gain Gwe Gyy.2 Gw.a +2 cB Frequency responce Gry. Gry.g Gry.a ~2 +2 dB Differential gain Dey-1 Dey-2 Dev-s Differential phase Dpy-1 Dpy.2 Dpy.3 % deg Linearity Lsv-1 bLsy-2 14 Lgy-a a7 40 43 Clock leakage (4 fsc) LoKay-1 Loxay-2 Lexay-a Clock leakage (fsc) Lexiy-1 15 Lexiy.2 LeKiy-3 mVrms a8 15 mVrms Noise Ny. Ny.g 16 Ny.g oro ol ope ol oye re eye el orfol oly ol ol oly ole jl oj op ol ell olor oylll o ll 0.5 2.0 mVrms Output impedance Zov-1 o o Zov-2 cb 17 Zora 250 4 Delay time Toy-1 Tov-2 b 18 Tov-3 FP Hao; aioyopea elo; sia folaialolaiploefael aloe foalole|eloloal el ole ial ole oe,po a oe of a ool sa yoyo rep ole Poo ae Pope eo oe Poole pol ole poli ole pollo Plo a ola ae ylayse oa al el we iaiwol mi seiaol~el ela l~olielel~olorlpol|m le le |/ oe > ele ie) a 63.88 63.46 63.46 Test Conditions 1. Supply current with no signal input. 2. C-OUT voltage (center bias voltage) with no signal input. 3. Measure the C-OUT output with 350 mVp-p sine wave signals input to C-IN1] and C-IN2. C-OUT output [(mVp-p] 350 [m Vp-p] GVC = 20 log Test frequencies GVC-1 GVC-2 GVC-3 4.431395 MHz (PAL/GBI) 3.571628 MHz (PAL/M) 3.571628 MHz (NTSC/M) [dB] No. 4900-3/9LC89971, 89971M 4. Measure the comb depth from the C-OUT output with a 350 mVp-p sine wave signal of frequency fa input to C-IN1 and C-IN2 and with a frequency of fb input. . C-OUT cutput with fb input [mVp-p] [dB] Gain C-OUT output with fa input [mVp-p] (cB) CD = 20 log Test frequencies fa fb CD-1 4.431395 MHz 4.435303 MHz (PAL/GBI) CD-2 3.571628 MHz 3.575561 MHz (PAL/M) CD-3 3.571628 MHz 3.575561 MHz (NTSC/M) b Frequency (Hz) 5. Measure the C-OUT output with a 200 mVp-p sine wave signal input to C-IN1 and C-IN2 and with 500 mVp-p sine wave signal input and calculate the difference in the gains. Output for a 500 mVp-p input [mVp-p] / Output fora 200 mVp-p input [mVp-p] LNC = 20 tog ( 500 ImVp-p] 200 [mVp-p} ) (a) Test frequencies LNC-1 = 4.431395 MHz (PAL/GBI) LNC-2. 3.571628 MHz (PAL/M) LNC-3 3.571628 MHz (NTSC/M) 6. Measure the 4 fsc (14.3 MHz) and fsc (3.58 MHz) components in the C-OUT output with no input. 7. Measure the noise in the C-OUT output with no input. Measure the noise with a noise meter set up with a 200 kHz high-pass filler and a 5 MHz low-pass filter. 8. Let V1 be the C-OUT output with a 350 mVp-p sine wave inpul 10 C-IN1 and C-IN2 and SW3 set to a, and let V2 be the C-OUT output with $W3 set to b. V2 {mp-p] V1 [m Vp-p] Vi [mVp-p] Test frequencies ZOC-1 4.431395 MHz (PAL/GBI) ZOC-2 =. 3.571628 MHz (PAL/M) ZOC-3 3.571628 MHz (NTSC/M) ZOC = x 500 [2] 9. The C-OUT output delay time with respect to inputs to C-IN1. (the CCD 2.5 bit delay) 10. Y-OUT voltage (clamp voltage) with no signal input. 11. Measure the Y-OUT output with a 200 kHz 400 mVp-p sine wave input to Y-IN. Y-OUT output [mVp-p] 400 [(mVp-p] 12. Measure the Y-OUT output with a 200 kHz 200 mVp-p sine wave input to Y-IN and with a 3.3 MHz 200 mVp-p sine wave input. GVY = 20 log [dB} Y-OUT output with a 3.5 MHz input [mVp-p] Y-OUT output with a 200 kHz input [mVp-p] Note that V,j;,; should be adjusted so that the circuit is biased to the clamp level plus 250 mV. GFY = 20 log [dB] No. 4900-4/9LC89971, 89971M 13. Input a five-level step waveform (see the figure below) to Y-IN and measure the differential gain and differential phase in the Y-OUT output with a vector scope. [\ UU AU 14. Input a five-level step waveform (see the figure below) to Y-IN and measure the luminance level (Y) and the sync level (5) in the Y-OUT output. A03833 5 [mV] LS= Fimv] x 100 [%] a03B34 15. Measure the 4 fsc (14,3 MHz) and fsc (3.58 MHz) components in the Y-OUT output with no input. 16. Measure the noise in the Y-OUT output with no input. Measure the noise with a noise meter set up with a 200 kHz high-pass filter, a 4.2 MHz low-pass filter, and a 3.58 MHz trap filter. 17. Let V1 be the Y-OUT output with a 200 kHz 400 mVp-p sine wave input and SW4 set to c, and let V2 be the C-OUT output with SW4 set to b. V2 (mVp-p] - V1 [mVp-p] V1 [mVp-p) 18. The Y-OUT delay time with respect to Y-IN ZOY = x 500 [Q] No. 4900-5/9LC89971, 89971M Pin Assignment [LC8997 1] punosry indul OOA indjno JOVBEdWdd aseud Atddns s9mMo0g puna) Addns samo Indjno yinsp dn-dag indino yaq|o 35] b jouuaD Indyno jeubis SOUBUILIOIUD punass LC89971 Indu) 49019 indjno uonoeued ANG) puna indjno jeubis aoueullwin] punoig) induy jeubys | SOueUILUuN] fequey Z Indul jeubis SOURUIWUGYS Aiddns sem0d bindu yeubys SOUBUIWOY) punousy Top view A03630 Pin Assignment [LC89971M] puna indul ODA indine soyesBdW0> aseud Addns samod puns) Ayddns JeMog qndyno nop dn-daig Indjno yoo/9 55) b (Qqueg Indino jeubis SOUBUILUQIYD punor) LC89971M | @NI-9 m!| dO, [a] 3NI-9 [=| BSA induy 49015 indine ucg281103 Ang punos indino jeusis soueUnLN] pundaisy * 4yndui peuBis SOUeUILUT] Z lonucg Zz indu jeubls S2UBUIWOIYO Ajddns Janog 4 indy jeudis SSUBLIWOYD puna Top view A03860 No. 4900-6/9LC89971, 89971M Block Diagram Note * Pin numbers in parentheses are for the LC89971M. Center ccD C-INi 2 . bias 2.5 bits Pm cee elas (23)|e-ouT of c-rna| 4 Center - - w18S bin bias cop e CO oT" 12 bite: Auto-bias input circuit 1 switching CONT1/20 (22) CONT2 o r=... + - Y-IN| 6 (7) ba Le 908 bee Yo0UT : Input 6 bits switching 18 (193/AD 4 #2 veo IN]i3 fio e 14);COmMP FSC ouT pid 45) it (12); PC OUT CLK A03B34 Control Pin Function . Chrominance signal delay Luminance signal delay CONT! CONT2 Mode (representative example) (CCD bits) (CCD bits) Low Low PAL/GBI 2 H (1834.5) + 0H (2.5) 1 H(914) Low High PAL/M 2H (1822.5) + 0 H (2.5) 1 H (908) High Low - _ _ High High NTSC/M 1H (912.5) + 0H (2.5) 1H (908) Switching Voltage Levels Lowshigh Symbol min typ max Unit Low VL 0.3 0.0 0.5 Vv High Vu 2.0 5.0 6.0 Vv Note: Since the control pin has a built-in pull-down resistor (= 70 kQ), the pin will be set to the low state if left open. FSC OUT Pin Functlon This pin provides a buffer output for the clock signal input to the CLK pin. When used When unused 5V 19 (20) fsc output Fsc OUT 19 (20) Fs OUT agaBa2 Note: Since this pin has a built-in pull-up resistor, the pin voltage will go to the supply voltage and output will cease if left open. No. 4900-7/9LC89971, 89971M Test Circuit [LC89971] Signal generator Signal generator Clock Test Circuit [LC8997 Hl o.oter] in | G=buT CONTE Fac BUT AG G-tni VYoo C-IW@ CONT2 Y-IN O.0isF Yoo Vasu Leagg7i Vas y-ouT Vag Yop PC OUT VEO IN Yaa cone CLK ro~o 9 Vader cose 1M) , L al zo} 19 [is] a.36F 1,.baF 4 ma, + Le. oF ews Veg C-OUT GONTS Vas oc-rw. Yoo c-xn2 oon] o.00aF kc Foc 3.3aF to the our AD Yoo Veo Vop Pe GUT YCO IN Yeo oO Lceaes7im ro CONTR Yorn Yoe -0UT Yss coMP CLK at] Signal generator rey iz [0.0iaF je.o4aF ii Signal generator . bayer Lo i Clock No. 4900-8/9LCs9971, 89971M M@ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. @ Anyone purchasing any products described or contained herein for an above-mentioned use shalt: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim aor litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Bf Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1995. Specifications and information herein are subject to change without notice. No. 4900-9/9