1
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
(enlarged source interconnection)
TSDSON-8FL
8 D
7 D
6 D
5 D
S 1
S 2
S 3
G 4
MOSFET
OptiMOSTM5Power-Transistor,100V
Features
•Idealforhighfrequencyswitching
•OptimizedtechnologyforDC/DCconverters
•ExcellentgatechargexRDS(on)product(FOM)
•N-channel,Logiclevel
•100%avalanchetested
•Pb-freeplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplications
•Halogen-freeaccordingtoIEC61249-2-21
Table1KeyPerformanceParameters
Parameter Value Unit
VDS 100 V
RDS(on),max 9.6 mΩ
ID40 A
QOSS 30 nC
QG(0VB4.5V) 12 nC
Type/OrderingCode Package Marking RelatedLinks
BSZ096N10LS5 PG-TSDSON-8 FL 096N10L -
1) J-STD20 and JESD22
2
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Continuous drain current ID
-
-
-
-
-
-
40
39
11
A
VGS=10V,TC=25°C
VGS=10V,TC=100°C
VGS=10V,TA=25°C,RthJA=60K/W1)
Pulsed drain current2) ID,pulse - - 160 A TC=25°C
Avalanche energy, single pulse3) EAS - - 82 mJ ID=20A,RGS=25Ω
Gate source voltage VGS -20 - 20 V -
Power dissipation Ptot -
-
-
-
69
2.1 WTC=25°C
TA=25°C,RthJA=60K/W1)
Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category;
DIN IEC 68-1: 55/150/56
2Thermalcharacteristics
Table3Thermalcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Thermal resistance, junction - case RthJC - 1.1 1.8 K/W -
Device on PCB,
minimal footprint RthJA - - 62 K/W -
Device on PCB,
6 cm2 cooling area1) RthJA - - 60 K/W -
1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2) See Diagram 3 for more detailed information
3) See Diagram 13 for more detailed information
4
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
3Electricalcharacteristics
Table4Staticcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Drain-source breakdown voltage V(BR)DSS 100 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 1.1 1.7 2.3 V VDS=VGS,ID=36µA
Zero gate voltage drain current IDSS -
-
0.1
10
1
100 µA VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS - 10 100 nA VGS=20V,VDS=0V
Drain-source on-state resistance RDS(on) -
-
10.5
8.2
13.5
9.6 mΩVGS=4.5V,ID=10A
VGS=10V,ID=20A
Gate resistance1) RG- 1.2 1.8 Ω-
Transconductance gfs 22 44 - S |VDS|>2|ID|RDS(on)max,ID=20A
Table5Dynamiccharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Input capacitance1) Ciss - 1600 2100 pF VGS=0V,VDS=50V,f=1MHz
Output capacitance1) Coss - 250 320 pF VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance1) Crss - 12 21 pF VGS=0V,VDS=50V,f=1MHz
Turn-on delay time td(on) - 5.7 - ns VDD=50V,VGS=10V,ID=20A,
RG,ext=3Ω
Rise time tr- 4.6 - ns VDD=50V,VGS=10V,ID=20A,
RG,ext=3Ω
Turn-off delay time td(off) - 21 - ns VDD=50V,VGS=10V,ID=20A,
RG,ext=3Ω
Fall time tf- 5.3 - ns VDD=50V,VGS=10V,ID=20A,
RG,ext=3Ω
Table6Gatechargecharacteristics2)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Gate to source charge Qgs - 4.7 - nC VDD=50V,ID=20A,VGS=0to4.5V
Gate charge at threshold Qg(th) - 2.5 - nC VDD=50V,ID=20A,VGS=0to4.5V
Gate to drain charge1) Qgd - 4.1 6.1 nC VDD=50V,ID=20A,VGS=0to4.5V
Switching charge Qsw - 6.3 - nC VDD=50V,ID=20A,VGS=0to4.5V
Gate charge total1) Qg- 12 15 nC VDD=50V,ID=20A,VGS=0to4.5V
Gate plateau voltage Vplateau - 3.0 - V VDD=50V,ID=20A,VGS=0to4.5V
Gate charge total Qg- 22 - nC VDD=50V,ID=20A,VGS=0to10V
Output charge1) Qoss - 30 40 nC VDD=50V,VGS=0V
1) Defined by design. Not subject to production test
2) See ″Gate charge waveforms″ for parameter definition
5
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
Table7Reversediode
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Diode continuous forward current IS- - 40 A TC=25°C
Diode pulse current IS,pulse - - 160 A TC=25°C
Diode forward voltage VSD - 0.85 1.2 V VGS=0V,IF=20A,Tj=25°C
Reverse recovery time1) trr - 34 68 ns VR=50V,IF=20A,diF/dt=100A/µs
Reverse recovery charge1) Qrr - 29 58 nC VR=50V,IF=20A,diF/dt=100A/µs
1) Defined by design. Not subject to production test
6
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
4Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
TC[°C]
Ptot[W]
0 25 50 75 100 125 150 175
0
10
20
30
40
50
60
70
80
Ptot=f(TC)
Diagram2:Draincurrent
TC[°C]
ID[A]
0 25 50 75 100 125 150 175
0
5
10
15
20
25
30
35
40
45
50
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
VDS[V]
ID[A]
10-1 100101102103
10-1
100
101
102
103
1 µs
10 µs
100 µs
1 ms
10 ms
DC
ID=f(VDS);TC=25°C;D=0;parameter:tp
Diagram4:Max.transientthermalimpedance
tp[s]
ZthJC[K/W]
10-6 10-5 10-4 10-3 10-2 10-1 100
10-2
10-1
100
101
0.5
0.2
0.1
0.05
0.02
0.01
single pulse
ZthJC=f(tp);parameter:D=tp/T
7
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
Diagram5:Typ.outputcharacteristics
VDS[V]
ID[A]
012345
0
20
40
60
80
100
120
140
160
5 V
6 V
10 V
4.5 V
4 V
3.5 V
3 V
ID=f(VDS);Tj=25°C;parameter:VGS
Diagram6:Typ.drain-sourceonresistance
ID[A]
RDS(on)[mΩ]
0 20 40 60 80 100
0
4
8
12
16
20
4 V
4.5 V
5 V
5.5 V
6 V 7 V
10 V
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
VGS[V]
ID[A]
01234567
0
20
40
60
80
100
25 °C
150 °C
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj
Diagram8:Typ.forwardtransconductance
ID[A]
gfs[S]
0 10 20 30 40 50 60 70
0
10
20
30
40
50
60
70
80
gfs=f(ID);Tj=25°C
8
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
Diagram9:Drain-sourceon-stateresistance
Tj[°C]
RDS(on)[mΩ]
-60 -20 20 60 100 140 180
0
5
10
15
20
Typ
max
RDS(on)=f(Tj);ID=20A;VGS=10V
Diagram10:Typ.gatethresholdvoltage
Tj[°C]
VGS(th)[V]
-60 -20 20 60 100 140 180
0.0
0.5
1.0
1.5
2.0
2.5
360 µA
36 µA
VGS(th)=f(Tj);VGS=VDS
Diagram11:Typ.capacitances
VDS[V]
C[pF]
0 20 40 60 80
100
101
102
103
104
Ciss
Coss
Crss
C=f(VDS);VGS=0V;f=1MHz
Diagram12:Forwardcharacteristicsofreversediode
VSD[V]
IF[A]
0.0 0.5 1.0 1.5 2.0
100
101
102
103
25 °C
150 °C
25 °C max
150 °C max
IF=f(VSD);parameter:Tj
9
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
Diagram13:Avalanchecharacteristics
tAV[µs]
IAV[A]
10-1 100101102103
100
101
102
25 °C
100 °C
125 °C
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
Diagram14:Typ.gatecharge
Qgate[nC]
VGS[V]
0 5 10 15 20 25
0
1
2
3
4
5
6
7
8
9
10
20 V 80 V
50 V
VGS=f(Qgate);ID=20Apulsed;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Tj[°C]
VBR(DSS)[V]
-60 -20 20 60 100 140 180
90
95
100
105
110
VBR(DSS)=f(Tj);ID=1mA
Gate charge waveforms
10
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
5PackageOutlines
Figure1OutlinePG-TSDSON-8FL,dimensionsinmm/inches
11
OptiMOSTM5Power-Transistor,100V
BSZ096N10LS5
Rev.2.1,2016-04-21Final Data Sheet
RevisionHistory
BSZ096N10LS5
Revision:2016-04-21,Rev.2.1
Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2016-03-07 Release of final version
2.1 2016-04-21 Update Gate threshold voltage
TrademarksofInfineonTechnologiesAG
AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™,
EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™,
ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™,
PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™,
SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™.
TrademarksupdatedAugust2015
OtherTrademarks
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©2016InfineonTechnologiesAG
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respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication
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