50 MHz, Precision, Low Distortion,
Low Noise CMOS Amplifiers
AD8651/AD8652
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Bandwidth: 50 MHz @ 5 V
Low noise: 4.5 nV/√Hz
Offset voltage: 100 μV typical, specified over
entire common-mode range
Slew rate: 41 V/μs
Rail-to-rail input and output swing
Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC_N packaging
APPLICATIONS
Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADCs and DACs
Microwave link interface
Cell phone PA control
Video line drivers
Audio
PIN CONFIGURATIONS
NC
1
–IN
2
+IN
3
V
–4
NC
8
V
+
7
OUT
6
NC
5
NC = NO CONNECT
AD8651
TOP VIEW
(Not to Scale)
03301-001
O
UT A
1
–IN A
2
+IN A
3
V
–4
V
+
8
OUT B
7
–IN B
6
+IN B
5
AD8652
TOP VIEW
(Not to Scale)
03301-003
Figure 1. 8-Lead MSOP (RM-8) Figure 2. 8-Lead MSOP (RM-8)
NC
1
–IN
2
+IN
3
V
–4
NC
8
V
+
7
OUT
6
NC
5
NC = NO CONNECT
AD8651
TOP VIEW
(Not to Scale)
03301-002
OUT A
1
–IN A
2
+IN A
3
V
–4
V
+
8
OUT B
7
–IN B
6
+IN B
5
AD8652
TOP VIEW
(Not to Scale)
03301-004
Figure 3. 8-Lead SOIC_N (R-8) Figure 4. 8-Lead SOIC_N (R-8)
GENERAL DESCRIPTION
The AD865x family consists of high precision, low noise, low
distortion, rail-to-rail CMOS operational amplifiers that run
from a single-supply voltage of 2.7 V to 5.5 V.
The AD865x family is made up of rail-to-rail input and output
amplifiers with a gain bandwidth of 50 MHz and a typical
voltage offset of 100 μV across common mode from a 5 V
supply. It also features low noise—4.5 nV/√Hz.
The AD865x family can be used in communications
applications, such as cell phone transmission power control, fiber
optic networking, wireless networking, and video line drivers.
The AD865x family features the newest generation of DigiTrim®
in-package trimming. This new generation measures and
corrects the offset over the entire input common-mode range,
providing less distortion from VOS variation than is typical of
other rail-to-rail amplifiers. Offset voltage and CMRR are both
specified and guaranteed over the entire common-mode range
as well as over the extended industrial temperature range.
The AD865x family is offered in the narrow 8-lead SOIC
package and the 8-lead MSOP package. The amplifiers are
specified over the extended industrial temperature range
(−40°C to +125°C).
AD8651/AD8652
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configurations........................................................................... 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications..................................................................................... 14
Theory of Operation .................................................................. 14
Rail-to-Rail Output Stage...................................................... 14
Rail-to-Rail Input Stage......................................................... 14
Input Protection ..................................................................... 15
Overdrive Recovery ............................................................... 15
Layout, Grounding, and Bypassing Considerations.............. 15
Power Supply Bypassing........................................................ 15
Grounding............................................................................... 15
Leakage Currents.................................................................... 15
Input Capacitance .................................................................. 16
Output Capacitance ............................................................... 16
Settling Time........................................................................... 16
THD Readings vs. Common-Mode Voltage ...................... 16
Driving a 16-Bit ADC............................................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/06—Rev. B. to Rev. C
Changes to Figure 1 to Figure 4...................................................... 1
Changes to Figure 7 and Figure 9................................................... 6
Changes to Figure 23........................................................................ 9
Changes to Figure 53...................................................................... 14
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
9/04—Rev. A to Rev. B
Added AD8652 ....................................................................Universal
Change to General Description....................................................... 1
Changes to Electrical Characteristics ............................................. 3
Changes to Absolute Maximum Ratings........................................ 5
Change to Figure 23 .......................................................................... 9
Change to Figure 26 .......................................................................... 9
Change to Figure 36 ........................................................................ 11
Change to Figure 42 ........................................................................ 12
Change to Figure 49 ........................................................................ 13
Change to Figure 51 ........................................................................ 13
Inserted Figure 52............................................................................ 13
Change to Theory of Operation section....................................... 14
Change to Input Protection section.............................................. 15
Changes to Ordering Guide........................................................... 20
6/04—Rev. 0 to Rev. A
Change to Figure 18 .............................................................................8
Change to Figure 21 .............................................................................9
Change to Figure 29 .............................................................................10
Change to Figure 30 .............................................................................10
Change to Figure 43 .............................................................................12
Change to Figure 44 .............................................................................12
Change to Figure 47 .............................................................................13
Change to Figure 57 .............................................................................17
10/03 Revision 0: Initial Version
AD8651/AD8652
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = 2.7 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
AD8651 0 V ≤ VCM ≤ 2.7 V 100 350 V
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V 1.4 mV
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 1.6 mV
AD8652 0 V ≤ VCM ≤ 2.7 V 90 300 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 0.4 1.3 mV
Offset Voltage Drift TCVOS 4 V/°C
Input Bias Current IB 1 10 pA
–40°C ≤ TA ≤ +125°C 600 pA
Input Offset Current IOS 1 10 pA
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA
Input Voltage Range VCM –0.1 +2.8 V
Common-Mode Rejection Ratio CMRR
AD8651 V+ = 2.7 V, –0.1 V < VCM < +2.8 V 75 95 dB
–40°C ≤ TA ≤ +85°C, –0.1 V < VCM < +2.8 V 70 88 dB
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 65 85 dB
AD8652 V+ = 2.7 V, –0.1 V < VCM < +2.8 V 77 95 dB
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 73 90 dB
Large Signal Voltage Gain AVO RL = 1 kΩ, 200 mV < VO < 2.5 V 100 115 dB
R
L = 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C 100 114 dB
R
L = 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C 95 108 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 250 A, –40°C ≤ TA ≤ +125°C 2.67 V
Output Voltage Low VOL IL = 250 A, –40°C ≤ TA ≤ +125°C 30 mV
Short-Circuit Limit ISC Sourcing 80 mA
Sinking 80 mA
Output Current IO 40 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB
–40°C ≤ TA ≤ +125°C 74 93 dB
Supply Current ISY
AD8651 IO = 0 9 12 mA
–40°C ≤ TA ≤ +125°C 14.5 mA
AD8652 IO = 0 17.5 19.5 mA
–40°C ≤ TA ≤ +125°C 22.5 mA
INPUT CAPACITANCE CIN
Differential 6 pF
Common Mode 9 pF
DYNAMIC PERFORMANCE
Slew Rate SR G = 1, RL = 10 kΩ 41 V/s
Gain Bandwidth Product GBP G = 1 50 MHz
Settling Time, 0.01% G = ±1, 2 V step 0.2 s
Overload Recovery Time VIN × G = 1.48 V+ 0.1 s
Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 %
NOISE PERFORMANCE
Voltage Noise Density enf = 10 kHz 5 nV/√Hz
f = 100 kHz 4.5 nV/√Hz
Current Noise Density inf = 10 kHz 4 fA/√Hz
AD8651/AD8652
Rev. C | Page 4 of 20
V+ = 5 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
AD8651 0 V ≤ VCM ≤ 5 V 100 350 V
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V 1.4 mV
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 1.7 mV
AD8652 0 V ≤ VCM ≤ 5 V 90 300 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 0.4 1.4 mV
Offset Voltage Drift TCVOS 4 V/°C
Input Bias Current IB 1 10 pA
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA
Input Offset Current IOS 1 10 pA
–40°C ≤ TA ≤ +85°C 30 pA
–40°C ≤ TA ≤ +125°C 600 pA
Input Voltage Range VCM –0.1 +5.1 V
Common-Mode Rejection Ratio CMRR
AD8651 0.1 V < VCM < 5.1 V 80 95 dB
–40°C ≤ TA ≤ +85°C, 0.1 V < VCM < 5.1 V 75 94 dB
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 70 90 dB
AD8652 0.1 V < VCM < 5.1 V 84 100 dB
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 76 95 dB
Large Signal Voltage Gain AVO RL = 1 kΩ, 200 mV < VO < 4.8 V 100 115 dB
R
L = 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C 98 114 dB
R
L = 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C 95 111 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.97 V
Output Voltage Low VOL IL = 250 µA, –40°C ≤ TA ≤ +125°C 30 mV
Short-Circuit Limit ISC Sourcing 80 mA
Sinking 80 mA
Output Current IO 40 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB
–40°C ≤ TA ≤ +125°C 74 93 dB
Supply Current ISY
AD8651 IO = 0 9.5 14.0 mA
–40°C ≤ TA ≤ +125°C 15 mA
AD8652 IO = 0 17.5 20.0 mA
–40°C ≤ TA ≤ +125°C 23.5 mA
INPUT CAPACITANCE CIN
Differential 6 pF
Common Mode 9 pF
DYNAMIC PERFORMANCE
Slew Rate SR G = 1, RL = 10 kΩ 41 V/µs
Gain Bandwidth Product GBP G = 1 50 MHz
Settling Time, 0.01% G = ±1, 2 V step 0.2 s
Overload Recovery Time VIN × G = 1.2 V+ 0.1 s
Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 %
NOISE PERFORMANCE
Voltage Noise Density enf = 10 kHz 5 nV/√Hz
f = 100 kHz 4.5 nV/√Hz
Current Noise Density inf = 10 kHz 4 fA/√Hz
AD8651/AD8652
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3.
Parameter Rating
Supply Voltage 6.0 V
Input Voltage GND to VS + 0.3 V
Differential Input Voltage ±6.0 V
Output Short-Circuit Duration to GND Indefinite
Electrostatic Discharge (HBM) 4000 V
Storage Temperature Range
RM, R Package −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range
RM, R Package −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC_N (R) 158 43 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8651/AD8652
Rev. C | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
V
OS
(µV)
V
S
= ±2.5V
V
CM
= 0V
NUMBER OF AMPLIFIERS
–200
–160
–120
–80
–40
0
40
80
120
160
200
0
10
50
40
30
20
60
03301-005
Figure 5. Input Offset Voltage Distribution
V
OS
(µV)
–300
–200
200
100
0
–100
300
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±2.5V
V
CM
= 0V
0
3301-006
Figure 6. Input Offset Voltage vs. Temperature
NUMBER OF AMPLIFIERS
0
10
50
40
30
20
60
TCV
OS
(µV/°C)
01234567891011
V
S
= ±2.5V
V
CM
=0V
T
A
: –40°C TO +125°C
0
3301-007
Figure 7. TCVOS Distribution
V
OS
(µV)
–20
0
80
60
40
20
100
COMMON-MODE VOLTAGE (V)
0123456
V
S
= 5V
0
3301-008
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
INPUT BIAS CURRENT (pA)
0
500
400
300
200
100
TEMPERATURE (°C)
040 120100806020 140
V
S
= ±2.5V
0
3301-009
Figure 9. Input Bias Current vs. Temperature
SUPPLY CURRENT (mA)
0
10
8
6
4
2
SUPPLY VOLTAGE (V)
02 5431 6
0
3301-010
Figure 10. Supply Current vs. Supply Voltage
AD8651/AD8652
Rev. C | Page 7 of 20
SUPPLY CURRENT (mA)
6
7
11
10
9
8
12
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±2.5V
0
3301-011
Figure 11. Supply Current vs. Temperature
(
V
SY
–
V
OUT
) (mV)
0
100
400
300
200
500
CURRENT LOAD (mA)
0204060 1080 0
V
S
=±2.5V
V
OH
V
OL
0
3301-012
Figure 12. Output Voltage to Supply Rail vs. Load Current
OUTPUT SWING HIGH (V)
4.990
4.991
4.995
4.996
4.994
4.993
4.992
4.997
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= 5V
I
L
= 250µA
0
3301-013
Figure 13. Output Voltage Swing High vs. Temperature
OUTPUT SWING LOW (mV)
0
0.50
2.50
2.00
1.50
1.00
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= 5V
I
L
= 250µA
03301-014
Figure 14. Output Voltage Swing Low vs. Temperature
CMRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
10 1k 10M1M100k10k100
V
S
= ±2.5V
0
3301-015
Figure 15. CMRR vs. Frequency
CMRR (dB)
90
95
110
105
100
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±2.5V
0
3301-016
Figure 16. CMRR vs. Temperature
AD8651/AD8652
Rev. C | Page 8 of 20
CMRR (dB)
82
85
100
97
91
88
94
TEMPERATURE (°C)
–50 0 50 100 150
0
3301-017
Figure 17. CMRR vs. Temperature
PSRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M 100M
V
S
= ±2.5V
+PSRR
–PSRR
0
3301-018
Figure 18. PSRR vs. Frequency
PSRR (dB)
80
85
100
95
90
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±2.5V
0
3301-019
Figure 19. PSRR vs. Temperature
VOLTAGE NOISE DENSITY (nV/√Hz)
1
100
10
FREQUENCY (Hz)
10 1k 100k10k100
V
S
= ±2.5V
0
3301-020
Figure 20. Voltage Noise Density vs. Frequency
CURRENT NOISE DENSITY (fA/√Hz)
0
80
60
40
20
FREQUENCY (Hz)
100 1k 100k10k
V
S
= ±2.5V
0
3301-021
Figure 21. Current Noise Density vs. Frequency
V
S
= ±2.5V
V
IN
= 6.4V
V
OUT
V
IN
VOLTAGE (1V/DIV)
TIME (200µs/DIV)
0
0
3301-022
Figure 22. No Phase Reversal
AD8651/AD8652
Rev. C | Page 9 of 20
OPEN-LOOP GAIN (dB)
–20
0
20
40
60
80
100
120
140
PHASE (Degrees)
–180
–135
–90
–45
0
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M 100M
V
S
= ±2.5V
03301-023
Figure 23. Open-Loop Gain and Phase vs. Frequency
OPEN-LOOP GAIN (dB)
112
113
117
116
115
114
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±2.5V
R
L
= 1kΩ
03301-024
Figure 24. Open-Loop Gain vs. Temperature
60
70
130
120
110
100
90
80
140
OUTPUT VOLTAGE SWING FROM THE RAILS (mV)
0 100 150 250200
I
L
=4.2mA
I
L
=2.5mA
V
S
=±2.5V
I
L
=250µA
OPEN-LOOP GAIN (dB)
50
03301-025
Figure 25. Open-Loop Gain vs. Output Voltage Swing
G = 100
G = 10
G = 1
V
S
= ±2.5V
R
L
= 1MΩ
C
L
= 47pF
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
5k
–40
–20
20
0
60
40
50k 5M500k 50M 300M
0
3301-026
Figure 26. Closed-Loop Gain vs. Frequency
MAXIMUM OUTPUT SWING (V)
0
6
3
4
5
2
1
FREQUENCY (Hz)
100k 100M10M1M
V
S
= 5V
V
S
= 2.7V
0
3301-027
Figure 27. Maximum Output Swing vs. Frequency
V
S
= ±2.5V
C
L
= 47pF
A
V
= 1
VOLTAGE (1V/DIV)
TIME (100µs/DIV)
0
3301-028
Figure 28. Large Signal Response
AD8651/AD8652
Rev. C | Page 10 of 20
VS = ±2.5V
VIN = 200mV
AV = 1
VOLTAGE (100mV/DIV)
TIME (10µs/DIV)
0
3301-029
Figure 29. Small Signal Response
SMALL SIGN
A
L OVERSHOOT (%)
0
30
25
20
15
10
5
CAPACITANCE (pF)
020 6050403010
+OS
–OS
70
V
S
= ±2.5V
V
IN
= 200mV
A
V
= 1
0
3301-030
Figure 30. Small Signal Overshoot vs. Load Capacitance
V
S
= ±2.5V
V
IN
= 200mV
GAIN = –15
TIME (200ns/DIV)
–200mV
2.5V
0V
0V
0
3301-031
Figure 31. Negative Overload Recovery Time
V
S
= ±2.5V
V
IN
= 200mV
GAIN = –15
OUTPUT
INPUT
TIME (200ns/DIV)
0V
0V
2
00m
V
–2.5V
0
3301-032
Figure 32. Positive Overload Recovery Time
OUTPUT IMPEDANCE (Ω)
0
40
30
20
10
FREQUENCY (Hz)
10 1k 100k10k100
VS = ±2.5V
GAIN = 100
GAIN = 10
GAIN = 1
0
3301-033
Figure 33. Output Impedance vs. Frequency
V
OS
(µV)
V
S
= ±1.35V
V
CM
= 0V
NUMBER OF AMPLIFIERS
–200
–160
–120
–80
–40
0
40
80
120
160
200
0
10
50
40
30
20
60
03301-034
Figure 34. Input Offset Voltage Distribution
AD8651/AD8652
Rev. C | Page 11 of 20
V
OS
(µV)
–300
–200
200
100
0
–100
300
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±1.35V
V
CM
= 0V
0
3301-035
Figure 35. Input Offset Voltage vs. Temperature
INPUT OFFSET VOLTAGE (µV)
–20
0
60
40
20
80
INPUT COMMON-MODE VOLTAGE (V)
012
3
V
S
= 2.7V
0
3301-036
Figure 36. Input Offset Voltage vs. Common-Mode Voltage
SUPPLY CURRENT (mA)
6
7
10
9
8
11
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±1.35V
0
3301-037
Figure 37. Supply Current vs. Temperature
(
V
SY
–
V
OUT
) (mV)
0
100
400
300
200
500
CURRENT LOAD (mA)
0204060 1080 0
V
S
= ±1.35V
V
OH
V
OL
0
3301-038
Figure 38. Output Voltage to Supply Rail vs. Load Current
OUTPUT SWING HIGH (V)
2.690
2.691
2.695
2.696
2.694
2.693
2.692
2.697
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= 2.7V
I
L
= 250µA
0
3301-039
Figure 39. Output Voltage Swing High vs. Temperature
OUTPUT SWING LOW (mV)
0
0.50
3.00
2.50
1.50
1.00
2.00
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= 2.7V
I
L
= 250µA
0
3301-040
Figure 40. Output Voltage Swing Low vs. Temperature
AD8651/AD8652
Rev. C | Page 12 of 20
V
S
= ±1.35V
A
V
= 1
VOLTAGE (1V/DIV)
TIME (200µs/DIV)
0
3301-041
Figure 41. No Phase Reversal
V
S
= ±1.35V
C
L
= 47pF
A
V
= 1
VOLTAGE (500mV/DIV)
TIME (100µs/DIV)
0
3301-042
Figure 42. Large Signal Response
V
S
= ±1.35V
V
IN
= 200mV
C
L
= 47pF
A
V
= 1
VOLTAGE (100mV/DIV)
TIME (10µs/DIV)
0
3301-043
Figure 43. Small Signal Response
SMALL SIGN
A
L OVERSHOOT (%)
0
30
25
20
15
10
5
CAPACITANCE (pF)
020 6050403010
+OS
70
V
S
= ±1.35V
V
IN
= 200mV
–OS
0
3301-044
Figure 44. Small Signal Overshoot vs. Load Capacitance
VS = ±1.35V
VIN = 200mV
GAIN = –10
TIME (200ns/DIV)
–200mV
1.35V
0V
0V
0
3301-045
Figure 45. Negative Overload Recovery Time
VS = ±1.35V
VIN = 200mV
GAIN = –10
TIME (200ns/DIV)
0V
0V
200m
V
–1.35V
03301-046
Figure 46. Positive Overload Recovery Time
AD8651/AD8652
Rev. C | Page 13 of 20
CMRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
10 1k 10M1M100k10k100
V
S
= ±1.35V
0
3301-047
Figure 47. CMRR vs. Frequency
PSRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M
V
S
= ±1.35V
+PSRR
–PSRR
0
3301-048
Figure 48. PSRR vs. Frequency
OPEN-LOOP GAIN (dB)
–20
0
20
40
60
80
100
120
140
PHASE (Degrees)
–180
–135
–90
–45
0
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M 100M
V
S
= ±1.35V
03301-049
Figure 49. Open-Loop Gain and Phase vs. Frequency
A
VO
(dB)
108
110
120
118
116
114
112
TEMPERATURE (°C)
–50 0 50 100 150
V
S
= ±1.35V
R
L
= 1kΩ
0
3301-050
Figure 50. Open-Loop Gain vs. Temperature
G = 100
G = 10
G = 1
V
S
= ±1.35V
R
L
= 1MΩ
C
L
= 47pF
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
5k
–40
–20
20
0
60
40
50k 5M500k 50M 300M
0
3301-051
Figure 51. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
10M100 1k 10k 100k 1M
CHANNEL SEPA
R
A
TION (dB)
0
–20
–40
–60
–80
–100
–120
–140
V
IN
28mV p-p
V+
V–
V–
V+
–2.5V
+2.5V
V
OUT
R1
10kΩ
R2
100Ω
V
S
= ±2.5V
03301-052
Figure 52. Channel Separation vs. Frequency.
AD8651/AD8652
Rev. C | Page 14 of 20
APPLICATIONS
THEORY OF OPERATION
The AD865x family consists of voltage feedback, rail-to-rail
input and output precision CMOS amplifiers that operate from
2.7 V to 5.5 V of power supply voltage. These amplifiers use
Analog Devices, Inc. DigiTrim technology to achieve a higher
degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of Analog
Devices amplifiers, is a method of trimming the offset voltage of
the amplifier after it has been assembled. The advantage of
post-package trimming is that it corrects any offset voltages
caused by the mechanical stresses of assembly.
The AD865x family is available in standard op amp pinouts,
making DigiTrim completely transparent to the user. The input
stage of the amplifiers is a true rail-to-rail architecture, allowing
the input common-mode voltage range of the op amp to extend
to both positive and negative supply rails. The open-loop gain
of the AD865x with a load of 1 kΩ is typically 115 dB.
The AD865x can be used in any precision op amp application.
The amplifiers do not exhibit phase reversal for common-mode
voltages within the power supply. With voltage noise of
4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals,
the AD865x is a great choice for high resolution data
acquisition systems. Their low noise, sub-pA input bias current,
precision offset, and high speed make them superb preamps for
fast photodiode applications. The speed and output drive
capabilities of the AD865x also make the amplifiers useful in
video applications.
Rail-to-Rail Output Stage
The voltage swing of the output stage is rail-to-rail and is
achieved by using an NMOS and PMOS transistor pair con-
nected in a common source configuration. The maximum
output voltage swing is proportional to the output current, and
larger currents will limit how close the output voltage can get to
the proximity of the output voltage to the supply rail. This is a
characteristic of all rail-to-rail output amplifiers. With 40 mA of
output current, the output voltage can reach within 5 mV of the
positive and negative rails. At light loads of >100 kΩ, the output
swings within ~1 mV of the supplies.
Rail-to-Rail Input Stage
The input common-mode voltage range of the AD865x extends
to both positive and negative supply voltages. This maximizes
the usable voltage range of the amplifier, an important feature
for single-supply and low voltage applications. This rail-to-rail
input range is achieved by using two input differential pairs, one
NMOS and one PMOS, placed in parallel. The NMOS pair is active
at the upper end of the common-mode voltage range, and the
PMOS pair is active at the lower end of the common-mode range.
The NMOS and PMOS input stages are separately trimmed
using DigiTrim to minimize the offset voltage in both differen-
tial pairs. Both NMOS and PMOS input differential pairs are
active in a 500 mV transition region when the input common-
mode voltage is approximately 1.5 V below the positive supply
voltage. A special design technique improves the input offset
voltage in the transition region that traditionally exhibits a
slight VOS variation. As a result, the common-mode rejection
ratio is improved within this transition band. Compared to the
Burr Brown OPA350 amplifier, shown in Figure 53, the
AD865x, shown in Figure 54, exhibits much lower offset voltage
shift across the entire input common-mode range, including the
transition region.
COMMON-MODE VOLTAGE (V)
V
OS
(µV)
0
–600
–200
200
600
400
0
–400
21435
6
0
3301-053
Figure 53. Input Offset Distribution over Common-Mode
Voltage for the OPA350
COMMON-MODE VOLTAGE (V)
VOS (µV)
0
–600
–200
200
600
400
0
–400
21435
6
0
3301-061
Figure 54. Input Offset Distribution over Common-Mode
Input Protection for the AD865x
AD8651/AD8652
Rev. C | Page 15 of 20
Input Protection
As with any semiconductor device, if a condition exists for the
input voltage to exceed the power supply, the device input
overvoltage characteristic must be considered. The inputs of the
AD865x family are protected with ESD diodes to either power
supply. Excess input voltage energizes internal PN junctions in
the AD865x, allowing current to flow from the input to the
supplies. This results in an input stage with picoamps of input
current that can withstand up to 4000 V ESD events (human
body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of any amplifier. Differential
voltages greater than 7 V result in an input current of approximately
(| VCC – VEE | – 0.7 V)/RI, where RI is the resistance in series with
the inputs. For input voltages beyond the positive supply, the
input current is approximately (VIN – VCC – 0.7)/RI. For input
voltages beyond the negative supply, the input current is about
(VIN – VEE + 0.7)/RI. If the inputs of the amplifier sustain
differential voltages greater than 7 V or input voltages beyond
the amplifier power supply, limit the input current to 10 mA by
using an appropriately sized input resistor (RI), as shown in
Figure 55.
(| V
CC
–V
EE
|–0.7V)
30mA
FOR LARGE | V
CC
–V
EE
|
FOR V
IN
BEYOND
SUPPLY VOLTAGES
R
I
>
R
I
–V
IN
+
+V
O
30mA
(V
IN
–V
EE
+0.7V)
R
I
>
30mA
(V
IN
–V
EE
–0.7V)
R
I
>
+
–
AD865x
03301-054
Figure 55. Input Protection Method
Overdrive Recovery
Overdrive recovery is defined as the time it takes for the output
of an amplifier to come off the supply rail after an overload signal is
initiated. This is usually tested by placing the amplifier in a closed-
loop gain of 15 with an input square wave of 200 mV p-p while the
amplifier is powered from either 5 V or 3 V. The AD865x family
has excellent recovery time from overload conditions (see Figure 31
and Figure 32). The output recovers from the positive supply rail
within 200 ns at all supply voltages. Recovery from the negative rail
is within 100 ns at 5 V supply.
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Power supply pins can act as inputs for noise, so care must be
taken that a noise-free, stable dc voltage is applied. The purpose
of bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.
Bypassing schemes are designed to minimize the supply
impedance at all frequencies with a parallel combination of
capacitors of 0.1 μF and 4.7 μF. Chip capacitors of 0.1 μF (X7R
or NPO) are critical and should be as close as possible to the
amplifier package. The 4.7 μF tantalum capacitor is less critical
for high frequency bypassing, and, in most cases, only one is
needed per board at the supply inputs.
Grounding
A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and, therefore, the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.
The length of the high frequency bypass capacitor leads is
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents also flow from the
supplies, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, intended to be effective at lower
frequencies, the current return path distance is less critical.
Leakage Currents
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias current of the AD865x family. Any voltage differential
between the inputs and nearby traces sets up leakage currents
through the PC board insulator, for example 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem).
To significantly reduce leakages, put a guard ring (shield)
around the inputs and the input leads that are driven to the
same voltage potential as the inputs. This ensures that there is
no voltage potential between the inputs and the surrounding
area to set up any leakage currents. To be effective, the guard
ring must be driven by a relatively low impedance source and
should completely surround the input leads on all sides, above
and below, using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard
ring helps to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, may be necessary in
some instances.
AD8651/AD8652
Rev. C | Page 16 of 20
Input Capacitance
Along with bypassing and grounding, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, which in turn increases the amplifier gain, causing
peaking in the frequency response or oscillations. With the
AD865x, additional input damping is required for stability with
capacitive loads greater than 47 pF with direct input to output
feedback (see the Output Capacitance section).
Output Capacitance
When using high speed amplifiers, it is important to consider
the effects of the capacitive loading on amplifier stability.
Capacitive loading interacts with the output impedance of the
amplifier, causing reduction of the BW as well as peaking and
ringing of the frequency response. To reduce the effects of the
capacitive loading and allow higher capacitive loads, there are
two commonly used methods.
• As shown in Figure 56, place a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amplifier output. Heavy capacitive loads can reduce the
phase margin of an amplifier and cause the amplifier
response to peak or become unstable. The AD865x is able
to drive up to 47 pF in a unity gain buffer configuration
without oscillation or external compensation. However, if
an application requires a higher capacitive load drive when
the AD865x is in unity gain, the use of external isolation
networks can be used. The effect produced by this resistor
is to isolate the op amp output from the capacitive load.
The required amount of series resistance has been
tabulated in Table 5 for different capacitive loads. While
this technique improves the overall capacitive load drive
for the amplifier, its biggest drawback is that it reduces the
output swing of the overall circuit.
V
IN
000
3
2
U1
R
L
C
L
R
S
V
OUT
V
CC
03301-055
+
–
AD865x
V
+
V
–
Figure 56. Driving Large Capacitive Loads
Table 5. Optimum Values for Driving Large Capacitive Loads
CL R
S
100 pF 50 Ω
500 pF 35 Ω
1.0 nF 25 Ω
• Another way to stabilize an op amp driving a large capacitive
load is to use a snubber network, as shown in Figure 57. Because
there is not any isolation resistor in the signal path, this method
has the significant advantage of not reducing the output swing.
The exact values of RS and CS are derived experimentally. In
Figure 57, an optimum RS and CS combination for a capacitive
load drive ranging from 50 pF to 1 nF was chosen. For this,
RS = 3 Ω and CS = 10 nF were chosen.
2
00mV R
L
C
L
R
S
C
S
V
OUT
V
+
V
–
0
3301-056
+
–
AD865x
V
+
V
–
Figure 57. Snubber Network
Settling Time
The settling time of an amplifier is defined as the time it takes
for the output to respond to a step change of input and enter
and remain within a defined error band, as measured relative to
the 50% point of the input pulse. This parameter is especially
important in measurements and control circuits where amplifi-
ers are used to buffer A/D inputs or DAC outputs. The design of
the AD865x family combines a high slew rate and a wide gain
bandwidth product to produce an amplifier with very fast
settling time. The AD865x is configured in the noninverting
gain of 1 with a 2 V p-p step applied to its input. The AD865x
family has a settling time of about 130 ns to 0.01% (2 mV). The
output is monitored with a 10×, 10 M, 11.2 pF scope probe.
THD Readings vs. Common-Mode Voltage
Total harmonic distortion of the AD865x family is well below
0.0004% with any load down to 600 Ω. The distortion is a
function of the circuit configuration, the voltage applied, and
the layout, in addition to other factors. The AD865x family
outperforms its competitor for distortion, especially at
frequencies below 20 kHz, as shown in Figure 58.
THD + NOIS E (
)
0.0001
0.0002
0.0005
0.001
0.002
0.005
0.01
0.02
0.05
0.1
FRE QUENC Y (Hz)
V
SY
= +3.5V/–1.5V
V
OUT
= 2.0V p- p
20 50 100 500 20k5k2k1k
OPA350
AD8651
03301-057
Figure 58. Total Harmonic Distortion
AD8651/AD8652
Rev. C | Page 17 of 20
1µF
3
2
U1
IN
2.7nF
33ΩV
CC
5
V
1kΩ
10kΩ
10kΩ
1kΩ
AD7685
V
IN
0V TO 5V
f
IN
= 45kHz
03301-060
+
–
AD865x
V
+
V
–
V
IN
2V p-p
47pF
600Ω
V
OUT
+3.5V
–1.5V
03301-058
+
–
AD865x
Figure 59. THD + N Test Circuit
Figure 61. AD865x Driving a 16-Bit ADC
Driving a 16-Bit ADC
The AD865x family is an excellent choice for driving high
speed, high precision ADCs. The driver amplifier for this type
of application needs low THD + N as well as quick settling time.
Figure 61 shows a complete single-supply data acquisition
solution. The AD865x family drives the AD7685, a 250 kSPS,
16-bit data converter.1
Table 6. Data Acquisition Solution of Figure 60
Parameter Reading (dB)
THD + N 105.2
SFDR 106.6
2nd Harmonics 107.7
3rd Harmonics 113.6
The AD865x is configured in an inverting gain of 1 with a 5 V
single supply. Input of 45 kHz is applied, and the ADC samples
at 250 kSPS. The results of this solution are listed in Table 6.
The advantage of this circuit is that the amplifier and ADC can
be powered with the same power supply. For the case of
a noninverting gain of 1, the input common-mode voltage
encompasses both supplies.
1 For more information about the AD7685 data converter, go to
http://www.analog.com/Analog_Root/productPage/productHome/0%2C21
21%2CAD7685%2C00.html
f
SAMPLE
= 250kSPS
f
IN
= 45kHz
INPUT RANGE = 0V TO 5V
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
0
–160
–100
–120
–140
–80
–60
–40
–20
0
10 20 30 40 50 60 70 80 90 100 110 120
03301-059
Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC
AD8651/AD8652
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 62. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD8651/AD8652
Rev. C | Page 19 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8651ARM-REEL –40°C to +125°C 8-Lead MSOP RM-8 BEA
AD8651ARM-R2 –40°C to +125°C 8-Lead MSOP RM-8 BEA
AD8651ARMZ-REEL1 –40°C to +125°C 8-Lead MSOP RM-8 BEA#
AD8651ARMZ-R21 –40°C to +125°C 8-Lead MSOP RM-8 BEA#
AD8651AR –40°C to +125°C 8-Lead SOIC_N R-8
AD8651AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8651AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ-REEL1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8651ARZ-REEL71 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARMZ-R21 –40°C to +125°C 8-Lead MSOP RM-8 A05
AD8652ARMZ-REEL1 –40°C to +125°C 8-Lead MSOP RM-8 A05
AD8652ARZ1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARZ-REEL1 –40°C to +125°C 8-Lead SOIC_N R-8
AD8652ARZ-REEL71 –40°C to +125°C 8-Lead SOIC_N R-8
1 Z = Pb-free part; # denotes lead-free product may be top or bottom marked.
AD8651/AD8652
Rev. C | Page 20 of 20
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03301-0-8/06(C)