UG Series
5–1
Rev. B – 25 May. 98
Description
The UG series of ULCs is well suited for conversion of
medium- to-large sized CPLDs and FPGAs. Devices are
implemented in high-performance CMOS technology
with 0.6-µm (drawn) channel lengths, and are capable of
supporting flip-flop toggle rates of 350 MHz, operating
clock frequencies up to 150 MHz and input to output
delays as fast as 5 ns.
The architecture of the UG series allows for efficient
conversion of many PLD architectures and FPGA
device types. A compact RAM cell, along with the large
number of available gates allows the implementation of
RAM in FPGA architectures that support this feature, as
well as JTAG boundary-scan and scan-path testing.
Conversion to the UG series of ULC can provide a
significant reduction in operating power when
compared to the original PLD or FPGA. This is
especially true when compared to many PLD and CPLD
architecture devices, which typically consume 100 mA
or more even when not being clocked. The UG series has
a very low standby consumption of 0.4 nA/gate
typically, which would yield a standby current of 4 mA
on a 10,000 gate design. Operating consumption is a
strict function of clock frequency, which typically
results in a power reduction of 50% to 90% depending
on the device being compared.
The UG series provides several options for output
buffers, including a variety of drive levels up to 24 mA.
Schmitt trigger inputs are also an option. A number of
techniques are used for improved noise immunity and
reduced EMC emissions, including: several
independent power supply busses and internal
decoupling for isolation; slew rate limited outputs are
also available as required.
The UG series is designed to allow conversions of high
performance 3.3V devices as well as 5.0V devices.
Support of mixed supply conversions is also possible,
allowing optimal trade-offs between speed and power
consumption.
Features
High performance ULC family suitable for
medium- to large-sized CPLDs and FPGAs
Conversions to over 200,000 FPGA gates
Pin counts to over 300 pins
Any pin-out matched due to limited number of
dedicated pads
Advanced 0.6-µm (drawn)/0.45-µm (effective)
feature size
Triple-layer or dual-layer metal CMOS
technology
High speed performance:
– 250-ps typical cell delay
– 350-MHz toggle rate
Full range of packages: DIP, SOIC, LCC/PLCC,
PQFP/TQFP, PGA/PPGA
3.3V and/or 5.0V operation.
Low quiescent current: 0.4 nA/gate
Available in commercial, industrial, automotive,
military and space grades.
0.6µm ULC Series
UG Series
5–2 Rev. B – 25 May. 98
Product Outline
Part Number Full programmables Pads Equivalent FPGA Gates Maximum Drive
UG01 30 3300 N/A
UG04 48 7500 310
UG09 72 15800 790
UG14 88 24300 1210
UG20 104 34800 1740
UG33 130 46000 2880
UG42 146 58600 3660
UG52 162 63700 4550
UG70 188 85800 6130
UG90 212 108500 7750
UG120 244 145100 10360
UG140 264 156800 12250
Architecture
The basic element of the UG family is called a cell. One
cell can typically implement between two to three FPGA
gates. Cells are located contiguously through out the
core of the device, with routing resources provided in
two or three metal layers above the cells. Some cell
blockage does occur due to routing, and utilization will
be significantly greater with three metal routing than
two. The sizes listed in the Product Outline are
estimated usable amounts using three metal layers. I/O
cells are provided at each pad, and may be configured as
inputs, outputs, I/Os, VDD or VSS as required to match
any FPGA or PLD pinout. Special function cells and
pins are located in the corners which typically are
unused.
In order to improve noise immunity within the device,
separate VDD and VSS busses are provided for the
internal cells and the I/O cells.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or
Schmitt Trigger, with or without a pull up or pull down
resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 3 to 12 mA
according to the chosen option. 24mA achievable, using
2 pads.
Slew Rate Controlled Output Buffer
In this mode, the p- and n-output transistor commands
are delayed, so that they are never set “ON”
simultaneously, resulting in a low switching current and
low noise. These buffer are dedicated to very high load
drive.
3.3V Compatibility
The UG series of ULCs is fully capable of supporting
high-performance operation at 3.3V or 5.0V. The
performance specifications of any given ULC design
however, must be explicitly specified as 3.3V, 5.0V or
both.
Power Supply and Noise Protection
In order to improve the noise immunity of the UG series,
several mechanisms have been implemented inside the
UG devices. Two kinds of protection have been added:
one to limit the I/O buffer switching noise and the other
to protect the I/O buffers against the switching noise
coming from the core.
I/O buffers switching protection
Three features are implemented to limit the noise
generated by the switching current: The power supplies
of the input and output buffer are separated. The rise and
fall times of the output buffers can be controlled. The
number of buffers that are connected on the same power
supply line is limited.
UG Series
5–3
Rev. B – 25 May. 98
Core switching current protection
This noise disturbance is caused by a large number of
gates switching simultaneously. To allow this without
impacting the functionality of the circuit, three new
features have been added: Some decoupling capacitors
are integrated directly on the silicon to reduce the power
supply drop. A power supply network has been
implemented in the matrix. This solution lessens the
parasitic elements such as inductance and resistance and
constitutes an artificial VDD and VSS plane. One mesh
of the network supplies approximately 150 cells. A
low-pass filter has been added between the core and the
inputs of the output buffers. This limits the transmission
of the noise coming from the ground or the VDD supply
of the core via the output buffers.
Absolute Maximum Ratings
Supply Voltage (VDD) –0.5 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage (VIN) –0.5 V to VDD + 7.0 V. . . . . . . . . . . . . . . . . . .
Storage Temperature –65 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Range
VDD 5 V 5% or 3.3 V 5%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature
Commercial 0 to 70_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Industrial –40 to 85_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Military –55 to 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics
Parameter Symbol Base Part
TA = Commercial Min Typ Max Unit
Output Voltage
VOH IOH = 24, 12, 6, 3 depending on buffer 2.4
Output Voltage VOL IOL = –24, –12, –6, –3 depending on buffer 0.4
V
Input Voltage
VIH 2.0 V
Input Voltage VIL 0.8
VIN = VSS –5 –1
Input Leakage Current
IIX
VIN = VDD 1 5
Input Leakage Current IIX VIN = VSS, with pull-up –100 –40
µ
A
VIN = VDD, with pull-down 40 100
µA
Output Leakage Current IOZ VOUT = VSS or VDD –5 15
Output Short Circuit Current
IOS
VOUT = VDD 90 160
mA
Output Short Circuit Current IOS VOUT = VSS –130 –60 mA
Standby Current ICCSB VDD = 5.25 V, VIN = VSS 0.4 1 nA/Gate
Operating Current IDDOP 0.3 0.4 µA/Gate/
MHz
Input Capacitance CIN VDD = 5.0 V, VIN = 2.0 V 2.5
pF
Output Capacitance COUT VOUT = 2.0 V 2 pF
Notes:
a. IOH = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements.
UG Series
5–4 Rev. B – 25 May. 98
Internal Timing Characteristics
These timing parameters for selected macro cells are
provided for information only. Only pin-to-pin timing
characteristics are guaranteed for ULCs, and the actual
specification is determined by the original FPGA or
PLD data sheet plus any specific parameters that are
agreed to separately by TEMIC.
Conditions: VDD = 5 V, Typical Process, Statistical Wire Length. All delays measured at VIN/VOUT = 2.5 V.
Macro Type Parameter Symbol Min MaxaMaxbUnits
2-Input NAND NAND2 0.39 0.56
4-Input NAND NAND4
Propagation Time
tPD
0.68 0.88
Inverter INV Propagation Time tPD 0.41 0.68 ns
Inverting Tri State Buffer
TRISTAN
0.74 0.99
Inverting Tri-State Buffer TRISTAN Enable Time tEN 0.69 0.97
Setup Time tSU 0.60
Hold Time tH0.00
Resetable Latch
LATCHR
Pulse Width tPW
Resetable Latch LATCHR Propagation Time tDQ 0.97 1.25
Enable Time tEN 1.22 1.49
Reset Time tRN 0.87 1.10
Setup Time tSU 0.40
Hold Time tH0.00
D Flip-Flop with Reset FDFFR Pulse Width tPW 0.60
pp
Clock Delay Time tCQ 0.95 1.22
Reset Time tRN 0.81 0.94
TTL Com
p
atible In
p
ut
BUFINTTL
tPLH 0.80 0.95
TTL
Compatible
Input
Buffer BUFINTTL tPHL 0.68 0.74 ns
TTL Compatible I/O Buffer
BIOT12
tPLH 0.80 0.95
TTL
Compatible
I/O
Buffer
Input Mode BIOT12
Propagation Time
tPHL 0.68 0.74
Output Buffer
BOUT6
Propagation Time tPLH 2.97 8.18
Output Buffer BOUT6 tPHL 1.96 4.23
tPLH 2.49 6.42
TTL Compatible I/O Buffer
BIOT12
tPLH 1.74 3.47
TTL Compatible I/O Buffer BIOT12
Enable Time
tPZH 3.27 7.17
Enable Time tPZL 1.60 3.30
Propagation Time
tPLH 2.49 6.42
Tri State Output Buffer
B3STA12
Propagation Time tPHL 1.74 3.47
Tri-State Output Buffer B3STA12
Enable Time
tPZH 3.27 7.17
Enable Time tPZL 1.60 3.30
Notes
a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of BOUT6 is
20 pF, BIOT12 and B3STA12 are 30 pF.
b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer.
Loading of BOUT6 is 80 pF, BIOT12 and B3STA12 are 120 pF.
UG Series
5–5
Rev. B – 25 May. 98
Derating Factors: tP = KP x Kt x KV x tNOMINAL
Process
Process Best Nominal Worst
KP0.82 1.00 1.28
Ambient Temperature _C
TA–55 –40 0 25 70 85 125
KT0.74 0.79 0.92 1.00 1.15 1.20 1.32
Supply Voltage
VDD 2.7 3 3.13 3.3 3.47 3.6 4 4.5 4.75 5 5.25 5.5
KV1.89 1.66 1.58 1.49 1.41 1.35 1.23 1.1 1.05 1 0.96 0.93
External Timing Characteristics
(Over the Operating Range)
These timing parameters are provided for information
only. Actual pin-to-pin timing characteristics
guaranteed for ULCs are determined by the original
FPGA or PLD data sheet plus any specific parameters
that are agreed to separately by TEMIC.
Parameter
Symbol
SSO
M
i
n
Max
Un
i
t
Parameter Symbol Base Part SSO Min Typ Max Unit
UG01 5.0 7.5
UG04–UG09 6.0 9.0
Propagation Time tPD UG14–UG20 7.0 10.5
UG33–UG90 8.5 13.0
UG120–UG140 9.5 14.5
UG01 32 6.5 10.0
UG04–UG09 50 7.5 11.5
Clock Delay Time tCO UG14–UG20 100 8.5 13.0
ns
UG33–UG90 220 10.0 15.0 ns
UG120–UG140 300 11.0 16.5
Hold Time tH0.0
UG01 32 6.5 10.0
UG04–UG09 50 7.5 11.5
Output Enable Time tEN UG14–UG20 100 8.5 13.0
UG33–UG90 220 10.0 15.0
UG120–UG140 300 11.0 16.5
UG Series
5–6 Rev. B – 25 May. 98
Power Consumption
Static Power Consumption for UG Series ULCs
There are three main factors to consider:
– Leakage in the core:
–P
LC = VDD * ICCSB * number of used gates
– Leakage in inputs and tri-stated outputs:
–P
LIO = VDD * (IIX * N + IOZ * M)
– where: N = number of inputs
– M = number of tri-stated outputs
– Care must be taken to include the appropriate
figure for pins with pull-ups or pull-downs. In
practice, the static consumption calculation is
typically done to determine the standby current
of a device; in this case only those pins sourcing
current should be included, i.e. where VIN or
VOUT = VDD.
– Dc power dissipation in driving I/O buffers due to
resistive loads:
– In practice, the static consumption calculation is
typically done to determine the standby current
of a device, and under circumstances where all of
the outputs are tri-stated or in input mode. So this
term is zero.
– Global formula for static consumption:
–P
SB = PLC + PLIO
Dynamic Power Consumption for UG Series
ULCs
There are four main factors to consider:
– Static power dissipation is negligible compared to
dynamic and can be ignored.
– Dc power dissipation in I/O buffers due to resistive
loads:
–P
1
(mW) = VOL * Σn (DLn * IOLn) + ( VDD – VOH)
* Σn (DHn * IOHn)
– where: Σn is a summation over all of the outputs
and I/Os.
–I
OLn and IOHn are the appropriate values for
driver n
–D
Ln = percentage of time n is being driven to VOL
–D
Hn = percentage of time n is being driven to
VOH
– It is difficult to obtain an exact value for this
factor, since it is determined primarily by
external system parameters. However, in
practice this can be simplified to one of two cases
where the device is either driving CMOS loads or
driving TTL loads. CMOS loads can be
approximated as purely capacitive loads,
allowing this term to be treated as zero. TTL
loads source significant current in the low state,
but not the high state, allowing the second
summation to be ignored. If a 50% duty cycle is
assumed for dynamic outputs driving TTL loads,
this can be approximated as:
–P
1
(mW) = VOL * (Σn * IOLn/2 + Σm * IOLm) (TTL
loads)
– where n are dynamic outputs and m are static low
outputs.
– Dynamic power dissipation for the internal gates:
–P
2
(mW) = VDD * IDDOP * Σg (Nf * fg)/1000
– where: Nf = number of gates toggling at
frequency fg
–f
g
= clock frequency of internal logic in MHz
– Note: If the actual toggle rates are not known, a
rule of thumb is to assume that the average used
gate is toggling at one half of the input clock
frequency.
– Dynamic power dissipation in the outputs:
–P
3
(mW) = VDD2 * Σn fn * (COUT + Cn)/1000
– where: fn = clocking frequency in MHz of output
n
–C
n
= output load capacitance in pF of output n
–C
OUT = output capacitance from DC
Characteristics
– Global formula for dynamic consumption:
– P = P1 + P2 + P3
Example:
Static calculation
– A 100-pin ULC with 3000 used gates, 10 inputs,
20 I/Os in input mode, 40 outputs all tri-stated.
No pull-ups or pull-downs. Half of the pins are at
VDD, half at VSS. Input clock is not toggling. For
this example only the current calculation is
desired, so the VDD term in the equations is
dropped.
–P
LC = 1 * 3000 = 3 mA
–P
LIO = ((10 + 20) * 5 + 40 * 5)/2 = 105 mA
–P
SB = 3 + 105 = 108 mA
Dynamic Calculation
– We take a 16-bit resettable ripple counter which
is approximately 100 gates, operating at a clock
frequency of 33 MHz, which gives an average
clock frequency of 33 MHz/16 for each bit and
each output. There are no static outputs on this
device. Operation is at 5 V, and 6-mA outputs are
used and loaded at 25 pF. The output buffers are
driving CMOS loads.
UG Series
5–7
Rev. B – 25 May. 98
–P
1
= 0
–P
2
= 5 * 0.5 * 100 * 33/16/1000 = 0.5 mW
–P
3
= 52 * 16 * 33/16 * (25 + 2)/1000 = 22 mW
– P = 0 + 0.5 + 22 = 22.5 mW
Typical ULC Test Conditions
For AC specification purposes, an improved output
loading scheme has been defined for TEMIC high-drive
(24 mA), high-speed ULC devices. The schematic
below (Figure 4.) describes the typical conditions for
testing these ULC devices, using the standard loading
scheme commonly available on high-end ATE.
Compared to a no-load condition, this provides the
following advantages:
Output load is more representative of “real life”
conditions during transitions.
Transient energy is absorbed at the end of the line to
prevent reflections which would lead to inaccurate
ATE measurements.
Figure 4. Typical ULC Test Conditions
D.U.T.
12 mA
12 mA
1.5 V
Comp