1
LT1995
1995fb
–
+
4k
4k
–
+
2k
2k
1k
INPUT
RANGE
–15V TO 15V
1k
4k
LT1995
–15V
1995 TA01a
15V OUT
REF
M1 M2 M4
P1 P2 P4
4k
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
32MHz, 1000V/µs
Gain Selectable Amplifier
■
Internal Gain Setting Resistors
■
Pin Configurable as a Difference Amplifier,
Inverting and Noninverting Amplifier
■
Difference Amplifier:
Gain Range 1 to 7
CMRR > 65dB
■
Noninverting Amplifier:
Gain Range 1 to 8
■
Inverting Amplifier:
Gain Range –1 to –7
■
Gain Error: <0.2%
■
Slew Rate: 1000V/µs
■
Bandwidth: 32MHz (Gain = 1)
■
Op Amp Input Offset Voltage: 2.5mV Max
■
Quiescent Current: 9mA Max
■
Wide Supply Range: ±2.5V to ±15V
■
Available in 10-Lead MSOP and
10-Lead (3mm × 3mm) DFN Packages
■
Instrumentation Amplifier
■
Current Sense Amplifier
■
Video Difference Amplifier
■
Automatic Test Equipment
High Slew Rate Differential Gain of 1
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
DESCRIPTIO
U
The LT
®
1995 is a high speed, high slew rate, gain select-
able amplifier with excellent DC performance. Gains from
–7 to 8 with a gain accuracy of 0.2% can be achieved using
no external components. The device is particularly well
suited for use as a difference amplifier, where the excellent
resistor matching results in a typical common mode
rejection ratio of 79dB.
The amplifier is a single gain stage design similar to the
LT1363 and features superb slewing and settling charac-
teristics. Input offset of the internal operational amplifier
is less than 2.5mV and the slew rate is 1000V/µs. The
output can drive a 150Ω load to ±2.5V on ±5V supplies,
making it useful in cable driver applications.
The resistors have excellent matching, 0.2% maximum at
room temperature and 0.3% from –40°C to 85°C. The
temperature coefficient of the resistors is typically
–30ppm/°C. The resistors are extremely linear with volt-
age, resulting in a gain nonlinearity of 10ppm.
The LT1995 is fully specified at ±2.5V, ±5V and ±15V sup-
plies and from –40°C to 85°C. The device is available in
space saving 10-lead MSOP and 10-Lead (3mm × 3mm)
DFN packages. For a micropower precision amplifier with
precision resistors, see the LT1991 and LT1996.
Large-Signal Transient (G = 1)
1995 TA01b
2
LT1995
1995fb
SYMBOL PARAMETER CONDITIONS V
SUPPLY
MIN TYP MAX UNITS
GE Gain Error V
OUT
= ±12V, R
L
= 1k, G = 1 ±15V 0.05 0.2 %
V
OUT
= ±12V, R
L
= 1k, G = 2 ±15V 0.05 0.2 %
V
OUT
= ±12V, R
L
= 1k, G = 4 ±15V 0.05 0.2 %
V
OUT
= ±5V, R
L
= 150Ω, G = 1 ±15V 0.05 0.25 %
V
OUT
= ±2.5V, R
L
= 500Ω, G = 1 ±5V 0.05 0.2 %
V
OUT
= ±2.5V, R
L
= 150Ω, G = 1 ±5V 0.05 0.25 %
GNL Gain Nonlinearity V
OUT
= ±12V, R
L
= 1k, G = 1 ±15V 10 ppm
V
OS
Input Offset Voltage G = 1 (MS10) ±15V 1 5 mV
Referred to Input (Note 7) G = 1 (DD10) ±15V 1.5 9 mV
G = 2 (MS10) ±15V 0.7 4 mV
G = 2 (DD10) ±15V 1.2 6.8 mV
G = 4 (MS10) ±15V 0.6 3.75 mV
G = 4 (DD10) ±15V 0.9 5.6 mV
G = 1 (MS10) ±5V 1 5 mV
G = 1 (DD10) ±5V 1.4 9 mV
G = 1 (MS10) ±2.5V 1 5 mV
G = 1 (DD10) ±2.5V 1.3 9 mV
Difference Amplifier Configuration. TA = 25°C, VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Total Supply Voltage (V
+
to V
–
) .............................. 36V
Input Current (Note 2) ....................................... ±10mA
Output Short-Circuit Duration (Note 3) ........... Indefinite
Operating Temperature Range (Note 4) .. – 40°C to 85°C
Specified Temperature Range (Note 5) ... – 40°C to 85°C
ABSOLUTE MAXIMUM RATINGS
W
WW
U
(Note 1)
Storage Temperature Range
MS Package .................................... – 65°C to 150°C
DD Package ..................................... – 65°C to 125°C
Maximum Junction Temperature
MS Package ..................................................... 150°C
DD Package ..................................................... 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LT1995CDD
LT1995IDD
T
JMAX
= 125°C, θ
JA
= 160°C/W (NOTE 6)
EXPOSED PAD INTERNALLY CONNECTED TO V
S–
PCB CONNECTION OPTIONAL
PACKAGE/ORDER INFORMATION
W
UU
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1M1
M2
M4
VS+
OUT
P1
P2
P4
VS–
REF
+–
DD PART
MARKING*
LBJF
LBJF
ORDER PART
NUMBER
LT1995CMS
LT1995IMS
MS PART
MARKING*
LTBJD
LTBJD
1
2
3
4
5
P1
P2
P4
VS–
REF
10
9
8
7
6
M1
M2
M4
VS+
OUT
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
+–
T
JMAX
= 150°C, θ
JA
= 160°C/W (NOTE 6)
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LT1995
1995fb
SYMBOL PARAMETER CONDITIONS V
SUPPLY
MIN TYP MAX UNITS
V
OS_OA
Op Amp Input Offset Voltage G = 1 (MS10) ±2.5V, ±5V, ±15V 0.5 2.5 mV
(Note 10) G = 1 (DD10) ±2.5V, ±5V, ±15V 0.75 4.5 mV
e
n
Input Noise Voltage G = 1, f = 10kHz ±2.5V to ±15V 27 nV/√Hz
G = 2, f = 10kHz ±2.5V to ±15V 18 nV/√Hz
G = 4, f = 10kHz ±2.5V to ±15V 14 nV/√Hz
R
IN
Common Mode Input Resistance V
CM
= ±15V, G = 1 ±15V 4 kΩ
C
IN
Input Capacitance ±15V 2.5 pF
Input Voltage Range G = 1 ±15V ±15 ±15.5 V
±5V ±5±5.5 V
±2.5V ±1±1.5 V
CMRR Common Mode Rejection Ratio G = 1, V
CM
= ±15V ±15V 65 79 dB
Referred to Input G = 2, V
CM
= ±15V ±15V 71 84 dB
G = 4, V
CM
= ±15V ±15V 75 87 dB
G = 1, V
CM
= ±5V ±5V 65 73 dB
G = 1, V
CM
= ±1V ±2.5V 61 68 dB
PSRR Power Supply Rejection Ratio P1 = M1 = 0V, G = 1, V
S
= ±2.5V to ±15V 78 87 dB
V
OUT
Output Voltage Swing R
L
= 1k ±15V ±13.5 ±14 V
R
L
= 500Ω±15V ±13 ±13.5 V
R
L
= 500Ω±5V ±3.5 ±4V
R
L
= 500Ω±2.5V ±1.3 ±2V
I
SC
Short-Circuit Current G = 1 ±15V ±70 ±120 mA
SR Slew Rate G = –2, V
OUT
= ±12V, P2 = 0V ±15V 750 1000 V/µs
Measured at V
OUT
= ±10V
G = –2, V
OUT
= ±3.5V, P2 = 0V ±5V 450 V/µs
Measured at V
OUT
= ±2V
FPBW Full Power Bandwidth 10V Peak, G = –2 (Note 8) ±15V 16 MHz
3V Peak, G = –2 (Note 8) ±5V 24 MHz
HD Total Harmonic Distortion G = 1, f = 1MHz, R
L
= 1k, V
OUT
= 2V
P-P
±15V –81 dB
–3dB Bandwidth G = 1 ±15V 32 MHz
±5V 25 MHz
±2.5V 21 MHz
t
r
, t
f
Rise Time, Fall Time 10% to 90%, 0.1V, G = 1 ±15V 10 ns
±5V 15 ns
OS Overshoot 0.1V, G = 1, C
L
= 10pF ±15V 30 %
±5V 30 %
t
pd
Propagation Delay 50% V
IN
to 50% V
OUT
, 0.1V, G = 1 ±15V 9 ns
±5V 11 ns
t
s
Settling Time 10V Step, 0.1%, G = 1 ±15V 100 ns
5V Step, 0.1%, G = 1 ±5V 110 ns
∆G Differential Gain G = 2, R
L
= 150Ω±15V 0.06 %
∆θ Differential Phase G = 2, R
L
= 150Ω±15V 0.15 Deg
R
OUT
Output Resistance f = 1MHz, G = 1 ±15V 1.5 Ω
I
S
Supply Current G = 1 ±15V 7.1 9.0 mA
±5V 6.7 8.5 mA
Difference Amplifier Configuration. TA = 25°C, VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
4
LT1995
1995fb
SYMBOL PARAMETER CONDITIONS V
SUPPLY
MIN TYP MAX UNITS
GE Gain Error V
OUT
= ±12V, R
L
= 1k, G = 1 ±15V ●0.05 0.25 %
V
OUT
= ±12V, R
L
= 1k, G = 2 ±15V ●0.05 0.25 %
V
OUT
= ±12V, R
L
= 1k, G = 4 ±15V ●0.05 0.25 %
V
OUT
= ±2.5V, R
L
= 500Ω, G = 1 ±5V ●0.05 0.25 %
V
OUT
= ±2.5V, R
L
= 150Ω, G = 1 ±5V ●0.05 0.35 %
V
OS
Input Offset Voltage G = 1 (MS10) ±15V ●1.1 6.5 mV
Referred to Input (Note 7) G = 1 (DD10) ±15V ●1.5 11.5 mV
G = 2 (MS10) ±15V ●0.8 5.5 mV
G = 2 (DD10) ±15V ●1.2 9 mV
G = 4 (MS10) ±15V ●0.7 5 mV
G = 4 (DD10) ±15V ●0.9 7.5 mV
G = 1 (MS10) ±5V ●1 6.5 mV
G = 1 (DD10) ±5V ●1.4 11.5 mV
G = 1 (MS10) ±2.5V ●1 6.5 mV
G = 1 (DD10) ±2.5V ●1.3 11.5 mV
V
OS
TC Input Offset Voltage Drift G = 1 (MS10) ±15V ●10 26 µV/°C
Referred to Input (Note 9) G = 1 (DD10) ±15V ●10 35 µV/°C
V
OS_OA
Op Amp Input Offset Voltage G = 1 (MS10) ±2.5V, ±5V, ±15V ●0.55 3.25 mV
(Note 10) G = 1 (DD10) ±2.5V, ±5V, ±15V ●0.75 5.75 mV
Input Voltage Range G = 1 ±15V ●±15 ±15.5 V
±5V ●±5±5.5 V
±2.5V ●±1±1.5 V
CMRR Common Mode Rejection Ratio V
CM
= ±15V, G = 1 ±15V ●63 77 dB
Referred to Input V
CM
= ±15V, G = 2 ±15V ●69 83 dB
V
CM
= ±15V, G = 4 ±15V ●73 86 dB
V
CM
= ±5V, G = 1 ±5V ●62 72 dB
V
CM
= ±1V, G = 1 ±2.5V ●59 66 dB
PSRR Power Supply Rejection Ratio P1 = M1 = 0V, G = 1, V
S
= ±2.5V to ±15V ●76 86 dB
V
OUT
Output Voltage Swing R
L
= 1k ±15V ●±13.1 ±14 V
R
L
= 500Ω±15V ●±12.6 ±13.5 V
R
L
= 500Ω±5V ●±3.4 ±4V
R
L
= 500Ω±2.5V ●±1.2 ±2V
I
SC
Short-Circuit Current G = 1 ±15V ●±55 ±115 mA
SR Slew Rate G = –2, V
OUT
= ±12V, P2 = 0V ±15V ●600 900 V/µs
Measured at V
OUT
= ±10V
I
S
Supply Current G = 1 ±15V ●7.9 10.5 mA
±5V ●7.4 9.9 mA
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS V
SUPPLY
MIN TYP MAX UNITS
GE Gain Error V
OUT
= ±12V, R
L
= 1k, G = 1 ±15V ●0.05 0.3 %
V
OUT
= ±12V, R
L
= 1k, G = 2 ±15V ●0.05 0.35 %
V
OUT
= ±12V, R
L
= 1k, G = 4 ±15V ●0.05 0.35 %
V
OUT
= ±2.5V, R
L
= 500Ω, G = 1 ±5V ●0.05 0.3 %
V
OUT
= ±2.5V R
L
= 150Ω, G = 1 ±5V ●0.05 0.5 %
5
LT1995
1995fb
SYMBOL PARAMETER CONDITIONS V
SUPPLY
MIN TYP MAX UNITS
V
OS
Input Offset Voltage G = 1 (MS10) ±15V ●1.2 7.5 mV
Referred to Input (Note 7) G = 1 (DD10) ±15V ●1.6 13 mV
G = 2 (MS10) ±15V ●0.9 6 mV
G = 2 (DD10) ±15V ●1.2 10 mV
G = 4 (MS10) ±15V ●0.7 5.5 mV
G = 4 (DD10) ±15V ●0.9 8.5 mV
G = 1 (MS10) ±5V ●1.1 7.5 mV
G = 1 (DD10) ±5V ●1.4 13 mV
G = 1 (MS10) ±2.5V ●1.1 7.5 mV
G = 1 (DD10) ±2.5V ●1.5 13 mV
V
OS
TC Input Offset Voltage Drift G = 1 (MS10) ±15V ●10 26 µV/°C
Referred to Input (Note 9) G = 1 (DD10) ±15V ●10 35 µV/°C
V
OS_OA
Op Amp Input Offset Voltage G = 1 (MS10) ±2.5V, ±5V, ±15V ●0.6 3.75 mV
(Note 10) G = 1 (DD10) ±2.5V, ±5V, ±15V ●0.8 6.5 mV
Input Voltage Range G = 1 ±15V ●±15 ±15.5 V
±5V ●±5±5.5 V
±2.5V ●±1±1.5 V
CMRR Common Mode Rejection Ratio V
CM
= ±15V, G = 1 ±15V ●62 77 dB
Referred to Input V
CM
= ±15V, G = 2 ±15V ●68 83 dB
V
CM
= ±15V, G = 4 ±15V ●72 86 dB
V
CM
= ±5V, G = 1 ±5V ●61 72 dB
V
CM
= ±1V, G = 1 ±2.5V ●57 66 dB
PSRR Power Supply Rejection Ratio P1 = M1 = 0V, G = 1, V
S
= ±2.5V to ±15V ●74 86 dB
V
OUT
Output Voltage Swing R
L
= 1k ±15V ●±13 ±14 V
R
L
= 500Ω±15V ●±12.5 ±13.5 V
R
L
= 500Ω±5V ●±3.3 ±4V
R
L
= 500Ω±2.5V ●±1.1 ±2V
I
SC
Short-Circuit Current G = 1 ±15V ●±50 ±105 mA
SR Slew Rate G = –2, V
OUT
= ±12V, P2 = 0V ±15V ●550 900 V/µs
Measured at V
OUT
= ±10V
I
S
Supply Current G = 1 ±15V ●8.0 11.0 mA
±5V ●7.6 10.4 mA
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected by diodes connected to V
S+
and V
S–
.
If an input goes beyond the supply range, the input current should be
limited to 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1995C and LT1995I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 5: The LT1995C is guaranteed to meet specified performance from
0°C to 70°C. The LT1995C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1995I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: Thermal resistance (θ
JA
) varies with the amount of PC board metal
connected to the leads. The specified values are for short traces connected
to the leads. If desired, the thermal resistance can be reduced slightly in
the MS package to about 130°C/W by connecting the used leads to a
larger metal area. A substantial reduction in thermal resistance down to
about 50°C/W can be achieved by connecting the Exposed Pad on the
bottom of the DD package to a large PC board metal area which is either
open-circuited or connected to V
S–
.
Note 7: Input offset voltage is pulse tested and is exclusive of warm-up
drift. V
OS
and V
OS
TC refer to the input offset of the difference amplifier
configuration. The equivalent input offset of the internal op amp can be
calculated from V
OS_OA
= V
OS
• G/(G +1).
Note 8: Full Power bandwidth is calculated from the slew rate measure-
ment: FPBW = SR/2πV
P
.
Note 9: This parameter is not 100% tested.
Note 10: The input offset of the internal op amp is calculated from the
input offset voltage: V
OS_OA
= V
OS
• G/(G +1).
6
LT1995
1995fb
FREQUENCY (Hz)
1
OUTPUT IMPEDACNE (Ω)
10
100
1000
10k 1M 10M 100M
1995 G09
0.1
100k
V
S
= ±15V
T
A
= 25°C
G = 7
G = 1
TEMPERATURE (°C)
–50
OUTPUT SHORT-CIRCUIT CURRENT (mA)
80
100
120
25 75
1995 G08
60
40
–25 0 50 100 125
20
0
V
S
= ±5V
SOURCE
SINK
TIME AFTER POWER ON (MINUTES)
0
0
CHANGE IN INPUT OFFSET VOLTAGE (µV)
50
100
150
200
250
300
1234
1995 G07
5
G = 1
G = 7
V
S
= ±15V
T
A
= 25°C
MS PACKAGE
OUTPUT CURRENT (mA)
–50
OUTPUT VOLTAGE (V)
1995 G06
5025–25 0
V–
0.5
1.0
1.5
2.0
3.0
2.5
–1.5
–2.0
–1.0
V+
–0.5
VS = ±5V
25°C
–40°C
85°C
–40°C
85°C
25°C
SUPPLY VOLTAGE (±V)
0
OUTPUT VOLTAGE (V)
1995 G05
20
510 15
V
–
0.5
1.0
1.5
–1.5
–1.0
V
+
–0.5
T
A
= 25°C
R
L
= 500Ω
R
L
= 1k
R
L
= 500Ω
R
L
= 1k
RESISTIVE LOAD (kΩ)
0
CHANGE IN GAIN ERROR (%)
0.05
0.04
0.03
0.01
0.02
0
–0.01
–0.02
–0.03
–0.04
–0.05 8
1995 G04
213579
4610
G = 7
G = 2
V
S
= ±15V
T
A
= 25°C
V
OUT
= ±12V
G = 4
G = 1
FREQUENCY (kHz)
10
INPUT VOLTAGE NOISE (nV/√Hz)
100
0.01 1 10 100
1995 G03
1
0.1
1000 VS = ±15V
TA = 25°C
G = 1
G = 7
G = 2
G = 4
SUPPLY VOLTAGE (±V)
0
SUPPLY CURRENT (mA)
4
6
20
1995 G02
2
0510 15
10
8T
A
= 125°C
T
A
= 25°C
T
A
= –55°C
INPUT OFFSET VOLTAGE (mV)
–3.5
0
NUMBER OF UNITS (%)
10
25
–1.5 0.5 1.5
1995 G01
5
20
15
–2.5 –0.5 2.5 3.5
VS = ±15V
VCM = 0V
G = 1
MS PACKAGE
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current vs Supply Voltage
and Temperature Input Noise Spectral Density
Change in Gain Error
vs Resistive Load
Output Voltage Swing vs Supply
Voltage
Output Voltage Swing vs Load
Current
(Difference Amplifier Configuration)
Warm-Up Drift vs Time
Output Short-Circuit Current
vs Temperature Output Impedance vs Frequency
VOS Distribution
7
LT1995
1995fb
FREQUENCY (Hz)
1k
COMMON MODE REJECTION RATIO (dB)
60
80
100
10M
1995 G18
40
20
50
70
90
30
10
010k 100k 1M 100M
V
S
= ±15V
T
A
= 25°C
G = 1
FREQUENCY (MHz)
–15
0
–5
–10
20
15
10
5
1995 G17
VOLTAGE MAGNITUDE (dB)
1100
10
V
S
= ±15V
T
A
= 25°C
R
L
= ∞
G = –1
C = 200pF
C = 100pF
C = 50pF
C = 0pF
FREQUENCY (Hz)
100k
–2
GAIN (dB)
0
2
4
6
1M 10M 100M
1995 G16
–4
–6
–8
–10
8
10 T
A
= 25°C
R
L
= 1k
±2.5V ±15V
±5V
TEMPERATURE (°C)
–50
20
25
35
25 75
1995 G15
–25 0 50 100 125
30
50
45
40
35
–3dB BANDWIDTH (MHz)
OVERSHOOT (%)
–3dB BANDWIDTH
OVERSHOOT
CL = 15pF
VS = ±15V
VS = ±15V
VS = ±5V
VS = ±5V
G = –1
SUPPLY VOLTAGE (±V)
0
–3dB BANDWIDTH (MHz)
OVERSHOOT (%)
20
25
30
16
1995 G14
4812
218
610 14
42
41
40
40
35
T
A
= 25°C
G = –1
–3dB BANDWIDTH
OVERSHOOT
C
L
= 15pF
GAIN (V/V)
1
0
SETTLING TIME (ns)
20
60
80
100
140
235
1995 G13
40
120
78
46
V
S
= ±15V
T
A
= 25°C
∆V
OUT
= 10V
R
L
= 1k
0.1% SETTLING
SETTLING TIME (ns)
0
OUTPUT STEP (V)
10
8
6
2
4
0
–2
–4
–6
–8
–10 140
1995 G12
20 40 80 120
60 100 160
10mV 1mV
10mV 1mV
VS = ±15V
TA = 25°C
RL = 1k
G = –1
SETTLING TIME (ns)
0
OUTPUT STEP (V)
10
8
6
2
4
0
–2
–4
–6
–8
–10 140
1995 G11
20 40 80 120 160
60 100 180
10mV 1mV
10mV 1mV
V
S
= ±15V
T
A
= 25°C
R
L
= 1k
G = 1
FREQUENCY (Hz)
GAIN (dB)
20
18
16
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
10k 1M 10M 100M
1995 G10
100k
G = 7
G = 4
G = 2
G = 1
V
S
= ±15V
T
A
= 25°C
R
L
= 1k
Frequency Response vs Supply
Voltage (G = 1, G = –1)
Frequency Response
vs Capacitive Load
Common Mode Rejection Ratio
vs Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(Difference Amplifier Configuration)
Gain vs Frequency
–3dB Bandwidth and Overshoot
vs Supply Voltage
–3dB Bandwidth and Overshoot
vs Temperature
Settling Time vs Output Step
(Non-Inverting)
Settling Time vs Output Step
(Inverting)
Settling Time vs Gain
(Non-Inverting)
8
LT1995
1995fb
SUPPLY VOLTAGE (V)
0
0
DIFFERENTIAL PHASE (DEG)
DIFFERENTIAL GAIN (%)
0.2
0.6
0.8
1.0
25 30
0.5
1995 G27
0.4
5 101520
0.2
0.1
0
0.3
0.4
DIFFERENTIAL
GAIN
DIFFERENTIAL
PHASE
T
A
= 25°C
R
L
= 150Ω
G = 2
FREQUENCY (MHz)
0.1
–100
DISTORTION (dBc)
–90
–80
–70
–60
–40
110
1995 G26
–50
2ND HARMONIC
3RD HARMONIC
V
S
= ±15V
V
OUT
= 2V
P-P
R
L
= 500Ω
G = 2
FREQUENCY (MHz)
0.1 1 10
OUTPUT VOLTAGE (VP-P)
10
9
8
7
6
5
4
3
2
1
0
1995 G25
G = 1
G = –1
VS = ±5V
TA = 25°C
HD <2%
FREQUENCY (MHz)
0.1 1 10
OUTPUT VOLTAGE (VP-P)
30
25
20
15
10
5
0
1995 G24
G = 1
G = –1
VS = ±15V
TA = 25°C
HD <2%
FREQUENCY (kHz)
0.01
0.0001
TOTAL HARMONIC DISTORTION (%)
0.001
0.01
10.1 10 100
1995 G23
G = –1
G = 1
TA = 25°C
Vo = 3VRMS
RL = 500Ω
INPUT LEVEL (VP-P)
0
0
SLEW RATE (V/µs)
200
600
800
1000
1400
210 14
1995 G22
400
1200
818 20
4612 16
TA = 25°C
VS = ±15V
G = –1
TEMPERATURE (°C)
–50
0
SLEW RATE (V/µs)
200
600
800
1000
50
1800
1995 G21
400
0
–25 75 100
25 125
1200
1400
1600
G = –2
V
S
= ±15V
V
OUT
= 27V
P-P
V
S
= ±5V
V
OUT
= 7V
P-P
SUPPLY VOLTAGE (±V)
0
SLEW RATE (V/µs)
600
800
1000
1995 G20
400
200
0510
1200
1400
1600
15
T
A
= 25°C
G = –1
V
OUT
= V
S+
– V
S–
– 3V
P-P
FREQUENCY (Hz)
1k
POWER SUPPLY REJECTION RATIO (dB)
50
+PSRR
70
90
10M
1995 G19
30
10
40
60
80
20
0
–10 10k 100k 1M 100M
–PSRR
V
S
= ±15V
T
A
= 25°C
G = 1
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(Difference Amplifier Configuration)
2nd and 3rd Harmonic Distortion
vs Frequency
Differential Gain and Phase
vs Supply Voltage
Slew Rate vs Supply Voltage
Power Supply Rejection Ratio
vs Frequency Slew Rate vs Temperature
Slew Rate vs Input Level
Total Harmonic Distortion vs
Frequency
Undistorted Output Swing vs
Frequency (±15V)
Undistorted Output Swing vs
Frequency (±5V)
9
LT1995
1995fb
CAPACITIVE LOAD
10pF
40
OVERSHOOT (%)
50
60
70
80
100pF 1000pF 0.01µF 0.1µF1µF
1995 G29
30
20
10
0
90
100
G = 1
G = 2 G = 4
G = 7
VS = ±5V
TA = 25°C
RL = ∞
CAPACITIVE LOAD
10pF
40
OVERSHOOT (%)
50
60
70
80
100pF 1000pF 0.01µF 0.1µF1µF
1995 G28
30
20
10
0
90
100 VS = ±15V
TA = 25°C
RL = ∞
G = 1
G = 2 G = 4
G = 7
Large-Signal Transient (G = 1) Large-Signal Transient (G = –1)
Large-Signal Transient
(Noninverting, G = 1, CL = 100pF)
V
S
= ±15V 100ns/DIV 1995 G33
R
L
= 1k
V
S
= ±15V 100ns/DIV 1995 G34
R
L
= 1k
V
S
= ±15V 100ns/DIV 1995 G35
R
L
= 1k
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(Difference Amplifier Configuration)
Small-Signal Transient (G = 1) Small-Signal Transient (G = –1)
Small-Signal Transient
(Noninverting, G = 1, CL = 100pF)
V
S
= ±15V 100ns/DIV 1995 G30
R
L
= 1k
V
S
= ±15V 100ns/DIV 1995 G31
R
L
= 1k
V
S
= ±15V 100ns/DIV 1995 G32
R
L
= 1k
Capacitive Load Handling Capacitive Load Handling
10
LT1995
1995fb
UU
U
PI FU CTIO S
P1 (Pin 1): Noninverting Gain-of-1 Input. Connects a 4k
internal resistor to the op amp’s noninverting input.
P2 (Pin 2): Noninverting Gain-of-2 Input. Connects a 2k
internal resistor to the op amp’s noninverting input.
P4 (Pin 3): Noninverting Gain-of-4 Input. Connects a 1k
internal resistor to the op amp’s noninverting input.
V
S–
(Pin 4): Negative Supply Voltage.
REF (Pin 5): Reference Voltage. Sets the output level when
the difference between the inputs is zero. Connects a 4k
internal resistor to the op amp’s non inverting input.
OUT (Pin 6): Output Voltage. V
OUT
= V
REF
+ 1 • (V
P1
– V
M1
)
+ 2 • (V
P2
– V
M2
) + 4 • (V
P4
– V
M4
).
V
S+
(Pin 7): Positive Supply Voltage.
M4 (Pin 8): Inverting Gain-of-4 Input. Connects a 1k
internal resistor to the op amp’s inverting input.
M2 (Pin 9): Inverting Gain-of-2 Input. Connects a 2k
internal resistor to the op amp’s inverting input.
M1 (Pin 10): Inverting Gain-of-1 Input. Connects a 4k
internal resistor to the op amp’s inverting input.
(Difference Amplifier Configuration)
11
LT1995
1995fb
BLOCK DIAGRA
W
3P4 R
P4
= 1k
2P2 R
P2
= 2k
1P1 R
P1
= 4k
8M4 R
M4
= 1k
9M2 R
M2
= 2k
10
5
6
M1
REF
7
V
S+
4
V
S–
OUT
1995 BD
R
M1
= 4k R
FB
= 4k
R
FB
= 4k
0.3pF
–
+
0.3pF
0.5pF
0.5pF
APPLICATIO S I FOR ATIO
WUUU
Configuration Flexibility
The LT1995 combines a high speed precision operational
amplifier with eight ratio-matched on-chip resistors. The
resistor configuration and pinout of the device is shown in
the Block Diagram. The topology is extremely versatile and
provides for simple realizations of most classic functional
configurations including difference amplifiers, inverting
gain stages, noninverting gain stages (including Hi-Z
input buffers) and summing amplifiers. The LT1995 deliv-
ers load currents of at least 30mA, making it ideal for cable
driving applications as well.
The input voltage range depends on gain and configura-
tion. ESD diodes will clamp any input voltage that exceeds
the supply potentials by more than several tenths of a volt;
and the internal op amp input ports must remain at least
1.75V within the rails to assure normal operation of the
part. The output will swing to within one and a half volts of
the rails, which in low supply voltage and high gain
configurations will create a limitation on the usable input
range. It should be noted that while the internal op amp can
withstand transient differential input voltages of up to 10V
without damage, this does generate large supply current
increases (tens of mA) as required for high slew rates. If
the device is used with sustained differential input across
the internal op amp (such as when the output is clipping),
the average supply current will increase, excessive power
dissipation will result, and the part may be damaged (i.e.,
the LT1995 is not recommended for use in comparator
applications or with the output clipped).
Difference Amplifier
The LT1995 can be connected as a classic difference
amplifier with an output function given by:
VOUT = G • (VIN+ – VIN–) + VREF
12
LT1995
1995fb
APPLICATIO S I FOR ATIO
WUUU
As shown in Figure 1, the options for fixed gain G include:
1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pin-
strapping alone. With split-supply applications where the
output is to be ground referenced, the VREF input is simply
tied to ground. The input common mode voltage is
rejected by the high CMRR of the part within the usable
input range.
Inverting Gain Amplifier
The LT1995 can be connected as an inverting gain ampli-
fier with an output function given by:
V
OUT
= –(G • V
IN–
) + V
REF
As shown in Figure 1, the options for fixed gain G include:
1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pin
strapping alone. The V
IN+
connection used in the differ-
ence amp configuration is simply tied to ground (or a low
impedance potential equal to the input signal bias to create
an input “virtual ground”). With split-supply applications
where the output is to be ground referenced, the V
REF
input
is simply tied to ground as well.
Noninverting Gain Buffer Amplifier
The LT1995 can be connected as a high input impedance
noninverting gain buffer amplifier with an output function
given by:
V
OUT
= G • V
IN
As shown in Figure 2, the options for fixed gain G include:
1, 1.14, 1.2, 1.33, 1.4, 1.6, 2, 2.33, 2.66, 3, 4, 5, 6, 7 and
8, all achieved by pin strapping alone. With single supply
applications, the grounded M input pins may be tied to a
low impedance potential equal to the input signal bias to
create a “virtual ground” for both the input and output
signals. While there is no input attenuation from V
IN
to the
internal noninverting op amp port in these configurations,
the P connections vary to minimize offset by providing
balanced input resistances to the internal op amp.
Noninverting Gain Amplifier Input Attenuation
The LT1995 can also be connected as a noninverting gain
amplifier having an input attenuation network to provide a
wide range of additional noninverting gain options. In
combination with the feedback configurations for gains of
G shown in Figure 2 (connections to the M inputs), the P
and REF inputs may be connected to form several resistor
divider attenuation ratios A, so that a compound output
function is given by:
V
OUT
= A • G • V
IN
As shown in Figure 3, the options for fixed attenuation A
include 0.875, 0.857, 0.833, 0.8, 0.75, 0.714, 0.667, 0.625
and 0.571, all achieved by pin strapping alone. With just
the attenuation configurations of Figure 3 and the feed-
back configurations of Figure 2, seventy-three unique
composite gains in the range of 1 to 8 are available (many
options for gain below unity also exist). Figure 3 does not
include the additional pin-strap configurations offering A
values of 0.5, 0.429, 0.375, 0.333, 0.286, 0.25, 0.2, 0.167,
0.143 and 0.125, as these values tend to compromise the
low noise performance of the part and don’t generally
contribute many more unique gain options. It should be
noted that with these configurations some degree of
imbalance will generally exist between the effective resis-
tances R
P
and R
M
seen by the internal op amp input ports,
noninverting and inverting, respectively. Depending on
the specific combination of A and G, the following DC
offset error due to op amp input bias current (I
B
) should be
anticipated: The I
B
of the internal op amp is typically 0.6µA
and is prepackage tested to a limit of 2µA. Additional
output-referred offset = I
B
• (R
P
– R
M
) • G. In some
configurations, this could be as much as 1.7mV • G
additional output offset. The I
OS
of the internal op amp is
typically 120nA and is prepackage tested to a limit of
350nA. The Electrical Characteristics table includes the
effects of I
B
and I
OS
.
13
LT1995
1995fb
APPLICATIO S I FOR ATIO
WUUU
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 1.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 2.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 3.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 1.33
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 4.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 5.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 7.00
REF
1995 F01
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 6.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VIN–
VIN+
VOUT
VREF
–V
+V
6
4
5
7
LT1995
G = 1.67
REF
Figure 1. Difference (and Inverting) Amplifier Configurations
Table 1. Pin Use, Input Range, Input Resistance, Bandwidth in Difference Amplifier Configuration
GAIN 1 2 3 4 5 6 7
Use of P1/M1 V
IN
Open V
IN
Open V
IN
Open V
IN
Use of P2/M2 Open V
IN
V
IN
Open Open V
IN
V
IN
Use of P4/M4 Open Open Open V
IN
V
IN
V
IN
V
IN
Positive Input Range: V
REF
= 0V, V
S
= ±15V ±15V ±15V ±15V ±15V ±15V ±15V ±15V
Positive Input Range: V
REF
= 0V, V
S
= ±5V ±5V ±4.88V ±4.33V ±4.06V ±3.9V ±3.79V ±3.71V
Positive Input Range: V
REF
= 0V, V
S
= ±2.5V ±1.5V ±1.13V ±1V ±0.94V ±0.9V ±0.88V ±0.86V
Positive Input Resistance 8k 6k 5.33k 5k 4.8k 4.67k 4.57k
Minus Input Resistance 4k 2k 1.33k 1k 800Ω667Ω571Ω
Ref Input Resistance 8k 6k 5.33k 5k 4.8k 4.67k 4.57k
Input Common Mode Resistance, V
REF
= 0V 4k 3k 2.67k 2.5k 2.4k 2.33k 2.29k
Input Differential Mode Resistance, V
REF
= 0V 8k 4k 2.67k 2k 1.6k 1.33k 1.14k
–3dB Bandwidth 32MHz 27MHz 27MHz 23MHz 18MHz 16MHz 15MHz
14
LT1995
1995fb
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 1.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 1.14
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 1.33
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 1.40
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 1.20
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
1995 F02
7
LT1995
G = 1.60
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 2.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 2.33
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 2.66
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 6.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
1995 F02b
VIN
–V
+V
6
4
5
7
LT1995
G = 8.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 7.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 3.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 4.00
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
VIN
–V
+V
6
4
5
7
LT1995
G = 5.00
REF
APPLICATIO S I FOR ATIO
WUUU
Figure 2. Noninverting Buffer Amplifier Configurations (Hi-Z Input)
15
LT1995
1995fb
APPLICATIO S I FOR ATIO
WUUU
AC-Coupling Methods for Single Supply Operation
The LT1995 can be used in many single-supply applications
using AC-coupling without additional biasing circuitry.
AC-coupling the LT1995 in a difference amplifier configu-
ration (as in Figure 1) is a simple matter of adding coupling
capacitors to each input and the output as shown in the
example of Figure 5. The input voltage V
BIAS
applied to the
REF pin establishes the quiescent voltage on the input and
output pins. The V
BIAS
signal should have a low source
impedance to avoid degrading the CMRR (0.5Ω for
1dB CMRR change typically).
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.875
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.833
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.857
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.800
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.714
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.750
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS
A = 0.667
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
1995 F03
7
LT1995
A = 0.571
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
V
IN
*
–V
+V
6
4
5
7
LT1995
A = 0.625
REF
Figure 3. Noninverting Amplifier Input Attenuation Configurations (A > 0.5)
1
1
2
4
5
6
8
1995 F04
3
7
73
GAIN COMBINATION
NONINVERTING GAIN
Figure 4. Unique Noninverting Gain Configurations
16
LT1995
1995fb
Using the LT1995 as an AC-coupled inverting gain stage,
the REF pin and the relevant P inputs may all be driven from
a V
BIAS
source as depicted in the example of Figure 6, thus
establishing the quiescent voltage on the input and output
pins. The V
BIAS
signal will only have to source the bias
current (I
B
) of the noninverting input of the internal op amp
(0.6µA typically), so a high V
BIAS
source impedance (R
S
)
will cause the quiescent level of the amplifier output to
deviate from the intended V
BIAS
level by I
B
• R
S
.
In operation as a noninverting gain stage, the P and REF
inputs may be configured as a “supply splitter,” thereby
providing a convenient mid-supply operating point. Fig-
ure 7 illustrates the three attenuation configurations that
generate 50% mid-supply biasing levels with no external
components aside from the desired coupling capacitors.
As with the DC-coupled input attenuation ratios, A, a
compound output function including the feedback gain
parameter G is given by:
V
OUT
= A • G • V
IN
APPLICATIO S I FOR ATIO
WUUU
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
C
OUT
V
BIAS
V
IN–
+V
6
4
5
1995 F06
7
LT1995
REF
C
IN
Figure 6. AC-Coupled Inverting Gain Amplifier
General Configuration (G = 5 Example)
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
COUT
CIN
VIN
*
+V
6
4
*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS. ANY M
INPUTS SHOWN GROUNDED IN FIGURE 2 SHOULD INSTEAD BE CAPACITIVELY COUPLED TO GROUND
5
7
LT1995
A = 0.750
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
1995 F07
COUT
CIN
VIN
*
+V
6
4
5
7
LT1995
A = 0.500
REF
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
COUT
CIN
VIN
*
+V
6
4
5
7
LT1995
A = 0.667
REF
Figure 7. AC-Coupled Noninverting Amplifier Input Attenuation Configurations (Supply Splitting)
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
C
OUT
V
BIAS
V
IN+
V
IN–
+V
6
4
5
1995 F05
7
LT1995
REF
C
IN
C
IN
Figure 5. AC-Coupled Difference Amplifier
General Configuation (G = 5 Example)
17
LT1995
1995fb
APPLICATIO S I FOR ATIO
WUUU
If one of the A parameter configurations in Figure 3 is
preferred, or the use of an external biasing source is
desired, the P and REF input connections shown grounded
in a Figure 3 circuit may be instead driven by a V
BIAS
voltage to establish a quiescent operating point for the
input and output pins. The V
IN
connections of the Figure 3
circuit are then driven via a coupling capacitor. Any
grounded M inputs for the desired G configuration (refer
to Figure 2) must be individually or collectively
AC-coupled to ground. Figure 8 illustrates a complete
example circuit of an externally biased AC-coupled nonin-
verting amplifier. The V
BIAS
source impedance should be
low (a few ohms) to avoid degrading the inherent accuracy
of the LT1995. 0.013% of additional Gain Error for each
ohm of resistance on the REF pin is typical.
at room temperature, and to within 0.3% over tempera-
ture. The temperature coefficient of the resistors is typi-
cally –30ppm/°C. The resistors have been sized to accom-
modate 15V across each resistor, or in terms of power,
225mW in the 1k resistors, 113mW in the 2k resistors, and
56mW in the 4k resistors.
Power Supply Considerations
As with any high speed amplifier, the LT1995 printed
circuit layout should utilize good power supply decoupling
practices. Good decoupling will typically consist of one or
more capacitors employing the shortest practical inter-
connection traces and direct vias to a ground plane. This
practice minimizes inductance at the supply pins so the
impedance is low at the operating frequencies of the part,
thereby suppressing feedback or crosstalk artifacts that
might otherwise lead to extended settling times, fre-
quency response anomalies, or even oscillation. For high
speed parts like the LT1995, 10nF ceramics are suitable
close-in bypass capacitors, and if high currents are being
delivered to a load, additional 4.7µF capacitors in parallel
can help minimize induced power supply transients.
Because unused input pins are connected via resistors to
the input of the op amp, excessive capacitances on these
pins will degrade the rise time, slew rate, and step re-
sponse of the output. Therefore, these pins should not be
connected to large traces which would add capacitance
when not in use.
Since the LT1995 has a wide operating supply voltage
range, it is possible to place the part in situations of
relatively high power dissipation that may cause excessive
die temperatures to develop. Maximum junction tempera-
ture (T
J
) is calculated from the ambient temperature (T
A
)
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
CONFIGURATION EXAMPLE:
A = 0.625
G = 6.00
(V
OUT
/V
IN
= 3.75V)
C
OUT
V
BIAS
V
IN
+V
6
4
5
1995 F08
7
LT1995
REF
C
BYP
C
IN
Figure 8. AC-Coupled Noninverting Amplifier
with External Bias Source (Example)
Resistor Considerations
The resistors in the LT1995 are very well matched, low
temperature coefficient thin film based elements. Although
their absolute tolerance is fairly wide (typically ±5% but
±25% worst case), the resistor matching is to within 0.2%
18
LT1995
1995fb
APPLICATIO S I FOR ATIO
WUUU
and power dissipation (P
D
) as follows for a nominal PCB
layout:
T
J
= T
A
+ (P
D
• θ
JA
)
For example, in order to maintain a maximum junction
temperature of 150°C at 85°C ambient in an MS10 pack-
age, the power must be limited to 0.4W. It is important to
note that when operating at ±15V supplies, the quiescent
current alone will typically account for 0.24W, so careful
thermal management may be required if high load cur-
rents and high supply voltages are involved. By additional
copper area contact to the supply pins or effective thermal
coupling to extended ground plane(s), the thermal imped-
ance can be reduced to 130°C/W in the MS10 package. A
substantial reduction in thermal impedance of the DD10
package down to about 50°C/W can be achieved by
connecting the Exposed Pad on the bottom of the package
to a large PC board metal area which is either open-
circuited or connected to V
S–
.
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
10nF
47Ω
V
IN
+V
–V
6
4
CONFIGURATION EXAMPLE:
G = 1.14
5
1995 F09
7
LT1995
REF
Figure 9. Optional Frequency Compensation
Network for (1 ≤ G ≤ 2)
Frequency Compensation
The LT1995 comfortably drives heavy resistive loads such
as back-terminated cables and provides nicely damped
responses for all gain configurations when doing so.
Small capacitances are included in the on-chip resistor
network to optimize bandwidth in the basic difference gain
configurations of Figure 1. For the noninverting configura-
tions of Figure 2, where the gain parameter G is 2 or less,
significant overshoot can occur when driving light loads.
For these low gain cases, providing an RC output network
as shown in Figure 9 to create an artificial load at high
frequency will assure good damping behavior.
Figure 10. Step Response of Circuit in Figure 9
19
LT1995
1995fb
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
MSOP (MS) 0603
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
20
LT1995
1995fb
LT1995
G = 1
SENSE
OUTPUT
100mV/A
FLAG
OUTPUT
4A LIMIT
15V
15V TO –15V
0.1Ω
I
10k
1995 TA05
10k
LT6700-3
–
+
400mV
–15V
REF
P1
M1
R
S
0.2Ω
10nF
LT1995
G = 5
–15V
–15V
15V 10nF
15V
I
OUT
V
IN
1k
1995 TA04
100Ω
–
+
LT1880
REF
IRF9530
M4
M1
P1
P4
I
OUT
= V
IN
5 • R
S
M1
P1
LT1995
G = –1
LT1790-1.25
–1.25V
–3V
REF
1995 TA03
3V
1µF
1.25V
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
VOUT
IIN = 600nA
1995 TA02
VIN
–V
+V
6
4
5
7
LT1995
REF
© LINEAR TECHNOLOGY CORPORATION 2004
LT/LT 0805 REV B • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
High Input Impedance Precision Gain of 2 Configuration
TYPICAL APPLICATIO S
U
Tracking Negative Reference
0A to 2A Current Source Current Sense with Alarm
PART NUMBER DESCRIPTION COMMENTS
LT1363 70MHz, 1000V/µs Op Amp 50ns Settling Time to 0.1%, C
LOAD
Stable
LT1990 High Voltage Difference Amplifier ±250V Common Mode Voltage, Micropower, Pin Selectable G = 1, 10
LT1991 Precision Gain Selectable Amplifier Micropower, Precision, Pin Selectable G = –13 to 14
LTC1992 Fully Differential Amplifier Differential Input and Output, Rail-to-Rail Output, I
S
= 1.2mA, C
LOAD
Stable
to 10,000pF, Adjustable Common Mode Voltage
LTC6910-x Programmable Gain Amplifiers 3 Gain Configurations, Rail-to-Rail Input and Output
RELATED PARTS
10k
M4
M2
M1
P1
P2
P4
8
9
10
1
2
3
V
OUT
f
–3dB
= 27MHz
R
L
= 75Ω
220µF
47µF
47µF
V
IN
5V
6
4
5
1995 TA06
7
LT1995
+
+
+
75Ω
Single Supply Video Line Driver