Rev. 0.92 8/05 Copyright © 2005 by Silicon Laboratories Si3215
Si3215
PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC WITH
RINGING/BATTERY VOLTAGE GENERATION
Features
Applications
Description
The ProSLIC is a low-voltage CMOS device that provides a complete analog
telephone interface ideal for customer premise equipment (CPE) applications.
The ProSLIC integrates subscriber line interface circuit (SLIC), codec, and battery
generation functionality into a single CMOS integrated circuit. The integrated
battery supply continuously adapts its output voltage to minimize power and
enables the entire solution to be powered from a single 3.3 V (Si3215M only) or
5 V supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201
Linefeed Interface Chip or discrete component line feed. Si3215 features include
software-configurable 5 REN internal ringing up to 90 VPK, DTMF generation, and
a comprehensive set of telephony signaling capabilities including expanded
support of Japan and China country requirements. The ProSLIC is packaged in a
38-pin QFN and TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-
pin SOIC.
Functional Block Diagram
Performs all BORSCHT functions
Software-programmable internal balanced
ringing up to 90 VPK
(5 REN up to 4 kft, 3 REN up to 8 kft)
Integrated battery supply with dynamic
voltage output
On-chip dc-dc converter continuously
minimizes power in all operating modes
Entire solution can be powered from a
single 3.3 V or 5 V supply
3.3 to 35 V dc input range
Dynamic 0 to –94.5 V output
Low-cost inductor and high-efficiency
transformer versions supported
Software-programmable linefeed
parameters:
Ringing frequency, amplitude, cadence,
and waveshape
2-wire ac impedance and hybrid
Constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds and
filtering
Software-programmable signal
generation and audio processing:
Phase-continuous FSK (caller ID)
generation
Dual audio tone generators
Smooth and abrupt polarity reversal
µ-Law/A-Law and 16-bit linear PCM
audio
Extensive test and diagnostic features
Multiple voice loopback test modes
Real time dc linefeed measurement
GR-909 line test capabilities
SPI and PCM bus digital interfaces
Extensive programmable interrupts
100% software-configurable global
solution
Ideal for customer premise equipment
applications
Lead-free and RoHS-compliant packages
available
Voice-over-broadband systems:
DSL, cable, wireless
PBX/IP-PBX/key telephone systems
Terminal adapters:
ISDN, Ethernet, USB
Linefeed
Interface
Control
Interface
PCM
Interface
PLL
Gain/
Attenuation/
Filter
Tone
Generators
CompressionExpansion
Gain/
Attenuation/
Filter
Line
Feed
Control
Line
Status
DC-DC Converter Controller
Prog.
Hybrid
D/A ZS
A/D TIP
RING
CS
SCLK
SDO
SDI
DTX
DRX
FSYNC
PCLK
RESETINT Si3215
Discrete
Components
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
Ordering Information
See page 111.
Pin Assignments
Si3215
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35363738
15 16 17 18 19
24
23
22
21
20
QFN
DTX
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST
DCFF
DCDRV
SDITHRU
SDO
SDI
SCLK
CS
INT
PCLK
DRX
Si3215
2 Rev. 0.92
Si3215
Rev. 0.92 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1. Si3210 to Si3215 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.6. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.7. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.11. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.12. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
5. Pin Descriptions: Si3215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Si3215
4 Rev. 0.92
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter Symbol Value Unit
Si3215
DC Supply Voltage VDDD, VDDA1, VDDA2 –0.5 to 6.0 V
Input Current, Digital Input Pins IIN ±10 mA
Digital Input Voltage VIND –0.3 to (VDDD +0.3) V
Operating Temperature Range2TA–40 to 100 °C
Storage Temperature Range TSTG –40 to 150 °C
TSSOP-38 Thermal Resistance, Typical θJA 70 °C/W
QFN-38 Thermal Resistance, Typical θJA 35 °C/W
Continuous Power Dissipation2PD0.7 W
Si3201
DC Supply Voltage VDD –0.5 to 6.0 V
Battery Supply Voltage VBAT –104 V
Input Voltage: TIP, RING, SRINGE, STIPE pins VINHV (VBAT – 0.3) to (VDD + 0.3) V
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins VIN –0.3 to (VDD +0.3) V
Operating Temperature Range2TA–40 to 100 °C
Storage Temperature Range TSTG –40 to 150 °C
SOIC-16 Thermal Resistance, Typical3θJA 55 °C/W
Continuous Power Dissipation2PD
0.8 at 70 oCW
0.6 at 85 oC
Notes:
1. Permanent device damage may occur if these absolute maximum ratings are exceeded. Functional operation should
be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Operation above 125 oC junction temperature may degrade device reliability.
3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
Si3215
Rev. 0.92 5
Table 2. Recommended Operating Conditions
Parameter Symbol Test Condition Min*Typ Max*Unit
Ambient Temperature TAK-grade 0 25 70 oC
Ambient Temperature TAB-grade –40 25 85 oC
Si3215 Supply Voltage VDDD,VDDA1,
VDDA2
3.13 3.3/5.0 5.25 V
Si3201 Supply Voltage VDD 3.13 3.3/5.0 5.25 V
Si3201 Battery Voltage VBAT VBATH =V
BAT –96 — –10 V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated.
Product specifications are only guaranteed when the typical application circuit (including component tolerances) is
used.
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Test Condition Min Typ Max Unit
TX/RX Performance
Overload Level THD = 1.5% 2.5 — — VPK
Single Frequency Distortion12-wire – PCM or
PCM – 2-wire:
200 Hz–3.4 kHz
——–45dB
Signal-to-(Noise + Distortion) Ratio2200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT,
any ZAC
Figure 1 — —
Audio Tone Generator
Signal-to-Distortion Ratio2
0 dBm0, Active off-hook,
and OHT, any Zac
45 — — dB
Intermodulation Distortion — — –45 dB
Gain Accuracy22-wire to PCM, 1014 Hz –0.5 0 0.5 dB
PCM to 2-wire, 1014 Hz –0.5 0 0.5 dB
Gain Accuracy Over Frequency Figure 3,4 — —
Group Delay Over Frequency Figure 5,6 — —
Gain Tracking31014 Hz sine wave, refer-
ence level –10 dBm
signal level:
3 dB to –37 dB –0.25 — 0.25 dB
–37 dB to –50 dB –0.5 — 0.5 dB
–50 dB to –60 dB –1.0 — 1.0 dB
Round-Trip Group Delay at 1000 Hz — 1100 — µs
Gain Step Accuracy –6 dB to 6 dB –0.017 — 0.017 dB
Gain Variation with Temperature All gain settings –0.25 — 0.25 dB
Gain Variation with Supply VDDA =V
DDA = 3.3/5 V ±5% –0.1 — 0.1 dB
Si3215
6 Rev. 0.92
2-Wire Return Loss 200 Hz to 3.4 kHz 30 35 — dB
Transhybrid Balance 300 Hz to 3.4 kHz 30 — — dB
Noise Performance
Idle Channel Noise4C-Message Weighted — — 15 dBrnC
Psophometric Weighted — — –75 dBmP
3 kHz flat — — 18 dBrn
PSRR from VDDA RX and TX, DC to 3.4 kHz 40 — — dB
PSRR from VDDD RX and TX, DC to 3.4 kHz 40 — — dB
PSRR from VBAT RX and TX, DC to 3.4 kHz 40 — — dB
Longitudinal Performance
Longitudinal to Metallic or PCM
Balance
200 Hz to 3.4 kHz, βQ1,Q2 ≥
150, 1% mismatch
56 60 — dB
βQ1,Q2 =60 to 240543 60 — dB
βQ1,Q2 =300 to 800553 60 — dB
Using Si3201 53 60 — dB
Metallic to Longitudinal Balance 200 Hz to 3.4 kHz 40 — — dB
Longitudinal Impedance 200 Hz to 3.4 kHz at TIP or
RING
Register selectable
ETBO/ETBA
00
01
10
—
—
—
33
17
17
—
—
—
Ω
Ω
Ω
Longitudinal Current per Pin Active off-hook
200 Hz to 3.4 kHz
Register selectable
ETBO/ETBA
00
01
10
—
—
—
4
8
8
—
—
—
mA
mA
mA
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be
–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING
. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ3/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. Assumes normal distribution of betas.
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Test Condition Min Typ Max Unit
Si3215
Rev. 0.92 7
Figure 1. Transmit and Receive Path SNDR
Figure 2. Overload Compression Performance
123456789
1
2
3
4
5
6
7
8
9
0
2.6
Acceptable
Region
Fundamental Input Power (dBm0)
Fundamental
Output Power
(dBm0)
Si3215
8 Rev. 0.92
Figure 3. Transmit Path Frequency Response
Typical Response
Typical Response
Si3215
Rev. 0.92 9
Figure 4. Receive Path Frequency Response
Si3215
10 Rev. 0.92
Figure 5. Transmit Group Delay Distortion
Figure 6. Receive Group Delay Distortion
Si3215
Rev. 0.92 11
Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70°C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Loop Resistance Range RLOOP See note. 0 — 160 Ω
DC Loop Current Accuracy ILIM = 29 mA, ETBA = 4 mA –10 — 10 %
DC Open Circuit Voltage
Accuracy
Active Mode; VOC =48V,
VTIP – VRING
–4 — 4 V
DC Differential Output
Resistance
RDO ILOOP < ILIM —160— Ω
DC Open Circuit Voltage—
Ground Start
VOCTO IRING<ILIM; VRING wrt ground
VOC =48V
–4 — 4 V
DC Output Resistance—
Ground Start
RROTO IRING<ILIM; RING to ground — 160 — Ω
DC Output Resistance—
Ground Start
RTOTO TIP to ground 150 — — kΩ
Loop Closure/Ring Ground
Detect Threshold Accuracy
ITHR = 11.43 mA –20 — 20 %
Ring Trip Threshold
Accuracy
ITHR = 40.64 mA –10 — 10 %
Ring Trip Response Time User Programmable Register 70
and Indirect Register 23
———
Ring Amplitude VTR 5 REN load; sine wave;
RLOOP =160Ω, VBAT = –75 V
44 — — Vrms
Ring DC Offset ROS Programmable in Indirect
Register 6
0——V
Trapezoidal Ring Crest
Factor Accuracy
Crest factor = 1.3 –.05 — .05
Sinusoidal Ring Crest
Factor
RCF 1.35 — 1.45
Ringing Frequency Accuracy f = 20 Hz –1 — 1 %
Ringing Cadence Accuracy Accuracy of ON/OFF Times –50 — 50 ms
Calibration Time ↑CAL to ↓CAL Bit — — 600 ms
Power Alarm Threshold
Accuracy
At Power Threshold = 300 mW –25 — 25 %
Note: DC resistance round trip; 160 Ω corresponds to 2 kft 26 gauge AWG.
Si3215
12 Rev. 0.92
Table 5. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Differential Nonlinearity
(6-bit resolution)
DNLE –1/2 — 1/2 LSB
Integral Nonlinearity
(6-bit resolution)
INLE –1 — 1 LSB
Gain Error (voltage) — — 10 %
Gain Error (current) — — 20 %
Table 6. Si321x DC Characteristics, VDDA =V
DDD =5.0V
(VDDA, VDDD = 4.75 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDDD ——V
Low Level Input Voltage VIL ——0.3xV
DD
D
V
High Level Output Voltage VOH SDITHRU:IO=–4mA
SDO, DTX:IO=–8mA
VDDD – 0.6 — — V
DOUT: IO= –40 mA VDDD – 0.8 — — V
Low Level Output Voltage VOL SDITHRU:
IO=4mA
SDO,INT,DTX:IO=8mA
——0.4V
Input Leakage Current IL–10 — 10 µA
Table 7. Si321x DC Characteristics, VDDA =V
DDD =3.3V
(VDDA, VDDD = 3.13 to 3.47 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDDD —— V
Low Level Input Voltage VIL ——0.3xV
DD
D
V
High Level Output Voltage VOH SDITHRU: IO =–2 mA
SDO, DTX:IO=–4mA
VDDD – 0.6 — — V
DOUT: IO= –40 mA VDDD – 0.8 — — V
Low Level Output Voltage VOL SDITHRU:
IO=2mA
SDO,INT,DTX:IO=4mA
——0.4V
Input Leakage Current IL–10 — 10 µA
Si3215
Rev. 0.92 13
Table 8. Power Supply Characteristics
(VDDA, VDDD = 3.13 V to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter Symbol Test Condition Typ1Typ2Max Unit
Power Supply Current,
Analog and Digital
IA + IDSleep (RESET = 0) 0.1 0.13 0.3 mA
Open 33 42.8 49 mA
Active on-hook
ETBO = 4 mA, codec and Gm
amplifier powered down
37 53 68 mA
Active OHT
ETBO = 4 mA 57 72 83 mA
Active off-hook
ETBA = 4 mA, ILIM = 20 mA 73 88 99
mA
Ground-start 36 47 55 mA
Ringing
Sinewave, REN = 1, VPK = 56 V 45 55 65 mA
VDD Supply Current (Si3201) IVDD Sleep mode, RESET = 0 — 100 — µA
Open (high impedance) — 100 — µA
Active on-hook standby — 110 — µA
Forward/reverse active off-hook, no
ILOOP
, ETBO = 4 mA, VBAT =–24V
—1—mA
Forward/reverse OHT, ETBO = 4 mA,
VBAT =–70V
—1—mA
VBAT Supply Current3IBAT Sleep (RESET =0) — 0 — mA
Open (DCOF = 1) — 0 — mA
Active on-hook
VOC = 48 V, ETBO = 4 mA — 3 — mA
Active OHT
ETBO = 4 mA — 11 — mA
Active off-hook
ETBA = 4 mA, ILIM =20mA — 30 — mA
Ground-start — 2 — mA
Ringing
VPK_RING =56 V
PK,
sinewave ringing, REN = 1
—5.5— mA
VBAT Supply Slew Rate When using Si3201 — — 10 V/µs
Notes:
1. VDDD, VDDA =3.3V.
2. VDDD, VDDA =5.25V.
3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%,
the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC).
Si3215
14 Rev. 0.92
Table 9. Switching Characteristics—General Inputs
VDDA =V
DDA = 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL= 20 pF)
Parameter Symbol Min Typ Max Unit
Rise Time, RESET tr—— 20ns
RESET Pulse Width trl 100 — — ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH =V
D –
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 10. Switching Characteristics—SPI
VDDA =V
DDA = 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL= 20 pF
Parameter Symbol Test
Conditions Min Typ Max Unit
Cycle Time SCLK tc0.062 — — µs
Rise Time, SCLK tr— — 25 ns
Fall Time, SCLK tf— — 25 ns
Delay Time, SCLK Fall to SDO Active td1 — — 20 ns
Delay Time, SCLK Fall to SDO
Transition
td2 — — 20 ns
Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns
Setup Time, CS to SCLK Fall tsu1 25 — — ns
Hold Time, CS to SCLK Rise th1 20 — — ns
Setup Time, SDI to SCLK Rise tsu2 25 — — ns
Hold Time, SDI to SCLK Rise th2 20 — — ns
Delay Time between Chip Selects
(Continuous SCLK)
tcs 440 — — ns
Delay Time between Chip Selects
(Non-continuous SCLK)
tcs 220 — — ns
SDI to SDITHRU Propagation Delay td4 — 4 10 ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =V
DDD –0.4 V, VIL =0.4V
Si3215
Rev. 0.92 15
Figure 7. SPI Timing Diagram
Table 11. Switching Characteristics—PCM Highway Serial Interface
VD= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL= 20 pF
Parameter Symbol Test
Conditions Min 1Typ 1Max 1Units
PCLK Frequency 1/tc—
—
—
—
—
—
—
—
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PCLK Duty Cycle Tolerance tdty 40 50 60 %
PCLK Period Jitter Tolerance tjitter –120 — 120 ns
Rise Time, PCLK tr——25ns
Fall Time, PCLK tf——25ns
Delay Time, PCLK Rise to DTX Active td1 ——20ns
Delay Time, PCLK Rise to DTX
Transition
td2 ——20ns
Delay Time, PCLK Rise to DTX Tri-State2td3 ——20ns
Setup Time, FSYNC to PCLK Fall tsu1 25 — — ns
Hold Time, FSYNC to PCLK Fall th1 20 — — ns
Setup Time, DRX to PCLK Fall tsu2 25 — — ns
Hold Time, DRX to PCLK Fall th2 20 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL =0.4V
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
CS
SDI
th1
td3
SDO
td1 td2
tsu1
trtr
tc
tsu2 th2
tcs
tthru
Si3215
16 Rev. 0.92
Figure 8. PCM Highway Interface Timing Diagram
Figure 9. Si3215/Si3215M Application Circuit Using Si3201
PCLK
DRX
FSYNC
DTX
td1 td2
tsu2 th2
td3
tr
tc
tsu1
th1
tf
Si32014
Si3215/Si3215M
R15
243
C2
10 µF
C1
10 µF
R14
40.2k
C5
22nF
C6
22nF
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
TIP
RING
GND
VBAT
TIP
RING
VDDD
VDDA1
GNDD
GNDA
IREF
CAPP
CAPM
IGMP
IGMN
QGN
D
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM
Bus
VDDA2
INT
RESET
R5
200k
R281
R21
15
VDD
Protection
Circuit
C24
0.1 µF
C19
4.7 µF
R6
4.02k
R7
4.02k
VBATH
SVBAT
29
25
28
26
17
19
18
1
3
4
5
15
13
16
14
11
10
8
7
31
23
10
27
30
TEST 32
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
Q9
2N2222
C26
0.1 µF
R291
VCC
VCC
VCC
SDCL
SDCH
DC-DC Converter
Circuit
DCDRV
DCFF
VDC
VBAT VDC
SDCL
SDCH
DCDRV
DCFF
STIPDC
STIPAC
R262
40.2k
GND
R322
10k
VCC
Note 2
Note 1
9
8
34
33
C18
4.7 µF
R1
200k
15
20
C3
220 nF
R8
4.7k
R3
200k
21
16
C4
220 nF R9
4.7k
SRINGAC
SRINGDC
Notes:
1. Values and configurations for these
components can be derived from Table 19 or
from “AN45: Design Guide for the Si3210 DC-
DC Converter”.
2. Only one component per system needed.
3. All circuit ground should have a single-point
connection to the ground plane.
4. Si3201 bottom-side exposed pad should be
electrically and thermally connected to bulk
ground plane.
R2
196k
R4
196k
VDDA1
C30
10 µF
VDDA2 VDDD
C16
0.1 µF
C15
0.1 µF
C17
0.1 µF
10 µF
10 V
C31
47 µH
L2
Si3215
Rev. 0.92 17
Figure 10. Si3215 BJT/Inductor DC-DC Converter Circuit
Table 12. Si3215/Si3215M External Component Values
Component(s) Value Supplier
C1,C2 10 µF, 6 V Ceramic or 16 V Low Leakage Electrolytic, ±20% Murata, Nichicon URL1C100MD
C3,C4 220 nF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C5,C6 22 nF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C15,C16,C17,C24 0.1 µF, 6 V, Y5V, ±20% Murata, Johanson, Novacap, Venkel
C18,C19 4.7 µF Ceramic, 6 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C26 0.1 µF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C30, C31 10 µF, 6 V, Electrolytic, ±20% Panasonic
L2 47 µH, 150 A Coilcraft
R1,R3,R5 200 kΩ, 1/10 W, ±1%
R2,R4 196 kΩ, 1/10 W, ±1%
R6,R7 4.02 kΩ, 1/10 W, ±1%
R8,R9 4.7 kΩ, 1/10 W, ±1%
R14,R26* 40.2 kΩ, 1/10 W, ±1%
R15 243 Ω, 1/10 W, ±1%
R21 15 Ω, 1/4 W, ±5%
R28,R29 1/10 W, 1% (See AN45 or Table 17 for value selection)
R32* 10 kΩ, 1/10 W, ±5%
Q9 60 V, General Purpose Switching NPN ON Semi MMBT2222ALT1; Central
Semi CMPT2222A; Zetex FMMT2222
*Note: Only one component per system needed.
Q8
2N2222
Q7
FZT953
D1
ES1D
C9
10 µF
C252
10 µF
C10
0.1 µF
R191
R201
R181
R16
200
R17
F1
SDCH
SDCL
DCFF
DCDRV
GND
L1
VBAT
C142
0.1 µF
VDC
See Note 1
Si3215
Notes:
1. Values and configurations for these components can be derived
from Table 21 or from “AN45: Design Guide for the Si3210 DC-DC
Converter”.
2. Voltage rating for C14 and C25 must be greater than VDC.
See
Note 1
Si3215
18 Rev. 0.92
Table 13. Si3215 BJT/Inductor DC-DC Converter Component Values
Component(s) Value Supplier
C9 10 µF, 100 V, Electrolytic, ±20% Panasonic
C10 0.1 µF, 50 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C1410.1 µF, X7R, ±20% Murata, Johanson, Novacap, Venkel
C25110 µF, Electrolytic, ±20% Panasonic
R16 200 Ω, 1/10 W, ±5%
R17 1/10 W, ±5% (See AN452 or Table 19 for value selec-
tion)
R18 1/4 W, ±5% (See AN45 or Table 19 for value selection)
R19,R20 1/10 W, ±1% (See AN45 or Table 19 for value selection)
F1 Fuse Belfuse SSQ Series
D1 Ultra Fast Recovery 200 V, 1 A Rectifier General Semi ES1D; Central Semi
CMR1U-02
L1 1A, Shielded Inductor (See “AN45: Design Guide for the
Si3210 DC-DC Converter” or Table 19 for value selec-
tion)
API Delevan SPD127 series, Sum-
ida CDRH127 series, Datatronics
DR340-1 series, Coilcraft DS5022,
TDK SLF12565
Q7 120 V, High Current Switching PNP Zetex FZT953, FZT955, ZTX953,
ZTX955; Sanyo 2SA1552
Q8 60 V, General Purpose Switching NPN ON Semi MMBT2222ALT1,
MPS2222A; Central Semi
CMPT2222A; Zetex FMMT2222
Notes:
1. Voltage rating of this device must be greater than VDC.
2. “AN45: Design Guide for the Si3210 DC-DC Converter”.
Si3215
Rev. 0.92 19
Figure 11. Si3215M MOSFET/Transformer DC-DC Converter Circuit
Table 14. Si3215M MOSFET/Transformer DC-DC Converter Component Values
Component(s) Value Supplier
C9 10 µF, 100 V, Electrolytic, ±20% Panasonic
C1410.1 µF, X7R, ±20% Murata, Johanson, Novacap, Venkel
C25110 µF, Electrolytic, ±20% Panasonic
C27 470 pF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
R17 200 kΩ, 1/10 W, ±5%
R18 1/4 W, ±5% (See AN452 or Table 18 for value selection)
R19,R20 1/10 W, ±1% (See AN45 or Table 18
for value selection)
R22 22 Ω, 1/10 W, ±5%
F1 Fuse Belfuse SSQ Series
D1 Ultra Fast Recovery 200 V, 1A Rectifier General Semi ES1D; Central Semi
CMR1U-02
T1 Power Transformer Coiltronic CTX01-15275;
Datatronics SM76315;
Midcom 31353R-02
M1 100 V, Logic Level Input MOSFET Intl Rect. IRLL014N; Intersil
HUF76609D3S; ST Micro
STD5NE10L, STN2NE10L
Notes:
1. Voltage rating of this device must be greater than VDC.
2. “AN45: Design Guide for the Si3210 DC-DC Converter”.
D1
ES1D
C9
10uF
C25
2
10uF
R19
1
R20
1
R18
1
R22
22
R17
200k
F1
SDCH
SDCL
DCFF
DCDRV
GND
VBAT
C14
2
0.1uF
VDC
C27
470pF
M1
IRLL014N T11
NC
Note 1
Note 1
1
2
3
410
Notes:
1. Values and configurations for these components can be derived
from Table 20 or from “AN45: Design Guide for the Si3210 DC-DC Converter”.
2. Voltage rating for C14 and C25 must be greater than VDC.
Si3215M
6
Si3215
20 Rev. 0.92
Figure 12. Si3215/Si3215M Typical Application Circuit Using Discrete Components
Table 15. Si3215/Si3215M External Component Values—Discrete Solution
Component Value Supplier/Part Number
C1,C2 10 µF, 6 V Ceramic or 16 V Low Leakage Electrolytic,
±20%
Murata, Panasonic, Nichicon
URL1C100MD
C3,C4 220 nF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C5,C6 22nF, 100V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C7,C8 220 nF, 50 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C15,C16,C17 0.1 µF, 6 V, Y5V, ±20% Murata, Johanson, Novacap, Venkel
C26 0.1 µF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel
C30, C31 10 µF, 16 V, Electrolytic, ±20% Panasonic
L2 47 µH, 150 A Coilcraft
Q1,Q2,Q3,Q4 120 V, PNP, BJT Central Semi CMPT5401; ON Semi
MMBT5401LT1, 2N5401; Zetex
FMMT5401;
Fairchild 2N5401; Samsung 2N5410
Q5,Q6 120 V, NPN, BJT Central Semi CZT5551, ON Semi
2N5551;
Fairchild 2N5551; Phillips 2N5551
Si3215/Si3215M
R15
243
C2
10uF
C1
10uF
R14
40.2k
C5
22nF
C6
22nF
ITIPP
ITIPN
STIPE
IRINGP
IRINGN
SRINGE
R1
200k
R3
200k
TIP
RING
VDDD
VDDA1
GNDD
GNDA
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM Bus
VDDA2
INT
RESET
R5
100k
R28
1
R21
15
Protection
Circuit
GND
R2
100k
R4
100k
15
20
28
29
17
26
25
19
18
21
16
31
23
10
27
30
TEST 32
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
Q9
2N2222
C26
0.1uF
R29
1
VCC
VCC
SDCL
SDCH
DC-DC Converter
Circuit
DCDRV
DCFF
VDC
VBAT VDC
SDCL
SDCH
DCDRV
DCFF
STIPDC
STIPAC
R26
2
40.2k
GND
R32
2
10k
VCC
Note 2
Note 1
Notes:
1. Values and configurations for these
components can be derived from Table 19 or
from “AN45: Design Guide for the Si3210 DC-
DC Converter”.
2. Only one component per system needed.
3. All circuit grounds should have a single-point
connection to the ground plane.
4. Optional components to improve idle channel
noise
9
8
34
33
R7
80.6
C7
220nF
Q5
5551
Q3
5401
Q2
5401
R11
10
R12
5.1k
R6
80.6
C8
220nF
Q6
5551
Q4
5401
Q1
5401
R10
10
R13
5.1k
GND
C4
220nF R9
4.7k
SRINGAC
SRINGDC
C3
220nF
R8
4.7k
SVBAT
VDDA1
C30
10 µF
VDDA2 VDDD
C16
0.1 µF
C15
0.1 µF
C17
0. 1 µF
10 µF
10 V
C31
47 µH
L2
C334
0.1 µF
C344
0.1 µF
R104 (100k)
R105 (100k)
R102 (100k)
C324
0.1 µF
Si3215
Rev. 0.92 21
Figure 13. Si321x Optional Equivalent Q5, Q6 Bias Circuit3
Q9 NPN General Purpose BJT ON Semi MMBT2222ALT1,
MPS2222A; Central Semi
CMPT2222A; Zetex FMMT2222
R1,R3 200 kΩ, 1/10 W, ±1%
R2,R4,R5,
R102,R104,
R105
100 kΩ, 1/10 W, ±1%
R6,R7 80.6 Ω, 1/4 W, ±1%
R8,R9 4.7 kΩ, 1/10 W, ±1%
R10,R11 10 Ω, 1/10 W, ±5%
R12,R13 5.1 kΩ, 1/10 W, ±5%
R14,R26* 40.2 kΩ, 1/10 W, ±1%
R15 243 Ω, 1/10 W, ±1%
R21 15 Ω, 1/4 W, ±1%
R28,R29 1/10 W, ±1% (See AN45 or Table 17 for value selection)
R32* 10 kΩ, 1/10 W, ±5%
Note: Only one component per system needed.
Table 15. Si3215/Si3215M External Component Values—Discrete Solution (Continued)
R7
80.6
RRE
C7
100 nF
CRBN
Q4
5401
QTDN
C8
CTBN
100 nF
Q5
5551
QRP
R23
3.0k
RRBN0
R24
3.0k
RTBN0
Q3
5401
QRDN
R6
80.6
RTE
R12
5.1k
RRBN
R13
5.1k
RTBN
Q6
5551
QTN
Si3215
22 Rev. 0.92
The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For
this optional subcircuit, C7 and C8 are different in voltage and capacitance than the standard circuit. R23 and R24
are additional components.
Table 16. Si321x Optional Bias Component Values
Component Value Supplier/Part Number
C7,C8 100 nF, 100 V, X7R, ±20% Murata, Johanson, Venkel
R23,R24 3.0 kΩ, 1/10 W, ±5%
Table 17. Component Value Selection for Si3215/Si3215M
Component Value Comments
R28 1/10 W, 1% resistor
For VDD = 3.3 V: 26.1 kΩ
For VDD = 5.0 V: 37.4 kΩ
R28 = (VDD + VBE)/148 µA
where VBE is the nominal VBE for Q9
R29 1/10 W, 1% resistor
For VCLAMP = 80 V: 541 kΩ
For VCLAMP = 85 V: 574 kΩ
For VCLAMP = 100 V: 676 kΩ
R29 = VCLAMP/148 µA
where VCLAMP is the clamping voltage for VBAT
Table 18. Component Value Selection Examples for Si3215M
MOSFET/Transformer DC-DC Converter
VDC Maximum Ringing Load/Loop Resistance Transformer Ratio R18 R19, R20
3.3 V 3 REN/117 Ω1–2 0.06 Ω7.15 kΩ
5.0 V 5 REN/117 Ω1–2 0.10 Ω16.5 kΩ
12 V 5 REN/117 Ω1–3 0.6 Ω56.2 kΩ
24 V 5 REN/117 Ω1–4 2.1 Ω121 kΩ
Note: There are other system and software conditions that influence component value selection.
Please refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed information.
Table 19. Component Value Selection Examples for Si3215 BJT/Inductor DC-DC Converter
VDC Maximum Ringing Load/Loop Resistance L1 R17 R18 R19, R20
5V 3 REN/117Ω67 µH 150 Ω0.15 Ω16.5 kΩ
12 V 5 REN/117 Ω150 µH 162 Ω0.56 Ω56.2kΩ
24 V 5 REN/117 Ω220 µH 175 Ω2.0 Ω121 kΩ
Note: There are other system and software conditions that influence component value selection, so please refer to “AN45:
Design Guide for the Si3210 DC-DC Converter” for detailed information.
Si3215
Rev. 0.92 23
2. Functional Description
The ProSLIC® is a single, low-voltage CMOS device
that provides all the SLIC, codec, and signal generation
functions needed for a complete analog telephone
interface. The ProSLIC performs all battery,
overvoltage, ringing, supervision, codec, hybrid, and
test (BORSCHT) functions. Unlike most monolithic
SLICs, the Si3215 does not require externally-supplied
high-voltage battery supplies. Instead, it generates all
necessary battery voltages from a positive dc supply
using its own dc-dc converter controller. Two fully-
programmable tone generators can produce DTMF
tones, phase-continuous FSK (caller ID) signaling, and
call progress tones. The Si3201 linefeed interface IC
performs all high-voltage functions. As an option, the
Si3201 can also be replaced with low-cost discrete
components as shown in the typical application circuit in
Figure 12.
The ProSLIC is ideal for short loop applications, such as
terminal adapters, cable telephony, PBX/key systems,
wireless local loop (WLL), and voice-over-IP solutions.
The device meets all relevant LSSGR and CCITT
standards.
The linefeed provides programmable on-hook voltage,
programmable off-hook loop current, reverse battery
operation, loop or ground start operation, and on-hook
transmission ringing voltage. Loop current and voltage
are continuously monitored using an integrated A/D
converter. Balanced 5 REN ringing with or without a
programmable dc offset is integrated. The available
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
A complete audio transmit and receive path is
integrated, including ac impedance and hybrid gain.
These features are software-programmable, allowing
for a single hardware design to meet international
requirements. Digital voice data transfer occurs over a
standard PCM bus. Control data is transferred using a
standard SPI. The device is available in 38-pin QFN or
TSSOP packages.
2.1. Si3210 to Si3215 Differences
The Si3215 is very similar to the Si3210 in terms of its
operation. The complete functionality of the Si3215 is
covered in this data sheet. There are some hardware
and software differences between the Si3215 and the
Si3210 that are mentioned here for customers migrating
designs from the Si3210 to the Si3215.
2.1.1. Hardware Changes
The Si3215 adds China and Japan impedances. See
"2.7. Two-Wire Impedance Matching" on page 42.
Pulse metering and DTMF detection are removed
from the Si3215.
The pinout on the QFN package has changed. See
"5. Pin Descriptions: Si3215" on page 107.
External resistors R8 and R9 are changed from
470 Ω to 4.7 kΩ. See the typical application circuit
in Figure 12.
2.1.2. Software Changes
The sample rate for the two-tone oscillators has
changed from 8 kHz to 16 kHz; therefore, the audio
tone coefficient equation has changed. See "2.4.2.
Oscillator Frequency and Amplitude" on page 33 for
a complete description.
The Si3215 is automatically calibrated for gain
mismatch, and manual calibration is not required.
Refer to “AN35: Si321x User’s Quick Reference
Guide”.
The Indirect Registers have been remapped. When
porting code from the Si3210 to the Si3215, the
indirect register access function needs to be
modified. See "4. Indirect Registers" on page 101.
2.2. Linefeed Interface
The ProSLIC’s linefeed interface offers a rich set of
features and programmable flexibility to meet the
broadest applications requirements. The dc linefeed
characteristics are software-programmable; key current,
voltage, and power measurements are acquired in real
time and provided in software registers.
Si3215
24 Rev. 0.92
2.2.1. DC Feed Characteristics
The ProSLIC has programmable constant voltage and
constant current zones as depicted in Figure 14. Open
circuit TIP-to-RING voltage (VOC) defines the constant
voltage zone and is programmable from 0 V to 94.5 V in
1.5 V steps. The loop current limit (ILIM) defines the
constant current zone and is programmable from 20 mA
to 41 mA in 3 mA steps. The ProSLIC has an inherent
dc output resistance (RO) of 160 Ω.
Figure 14. Simplified DC Current/Voltage Linefeed
Characteristic
The TIP-to-RING voltage (VOC) is offset from ground by
a programmable voltage (VCM) to provide voltage
headroom to the positive-most terminal (TIP in forward
polarity states and RING in reverse polarity states) for
carrying audio signals. Table 20 summarizes the
parameters to be initialized before entering an active
state.
2.2.2. Linefeed Architecture
The ProSLIC is a low-voltage CMOS device that uses
either an Si3201 linefeed interface IC or low-cost
external components to control the high voltages
required for subscriber line interfaces. Figure 15 is a
simplified illustration of the linefeed control loop circuit
for TIP or RING and the external components used.
The ProSLIC uses both voltage and current sensing to
control TIP and RING. DC and AC line voltages on TIP
and RING are measured through sense resistors RDC
and RAC. The ProSLIC uses linefeed transistors QP and
QN to drive TIP and RING. QDN isolates the high-voltage
base of QN from the ProSLIC.
The ProSLIC measures voltage at various nodes in
order to monitor the linefeed current. RDC, RSE, and
RBAT provide access to these measuring points. The
sense circuitry is calibrated on-chip to guarantee
measurement accuracy with standard external
component tolerances. See "2.2.9. Linefeed
Calibration" on page 29 for details.
2.2.3. Linefeed Operation States
The ProSLIC linefeed has eight states of operation as
shown in Table 21. The state of operation is controlled
using the Linefeed Control register (direct Register 64).
The open state turns off all currents into the external
bipolar transistors and can be used in the presence of
fault conditions on the line and to generate Open Switch
Intervals (OSIs). TIP and RING are effectively tri-stated
with a dc output impedance of about 150 kΩ. The
ProSLIC can also automatically enter the open state if it
detects excessive power being consumed in the
external bipolar transistors. See "2.2.5. Power
Monitoring and Line Fault Detection" on page 27 for
more details.
In the forward active and reverse active states, linefeed
circuitry is on, and the audio signal paths are powered
down.
In the forward and reverse on-hook transmission states,
audio signal paths are powered up to provide data
transmission during an on-hook loop condition.
The TIP Open state turns off all control currents to the
external bipolar devices connected to TIP and provides
an active linefeed on RING for ground start operation.
The RING Open state provides similar operation with
the RING drivers off and TIP active.
The ringing state drives programmable ringing
waveforms onto the line.
Table 20. Programmable Ranges of DC
Linefeed Characteristics
Parameter Programmable
Range
Default
Value
Register
Bits
Location*
ILIM 20 to 41 mA 20 mA ILIM[2:0] Direct
Register 71
VOC 0 to 94.5 V 48 V VOC[5:0] Direct
Register 72
VCM 0 to 94.5 V 3 V VCM[5:0] Direct
Register 73
*Note: The ProSLIC uses registers that are both directly and
indirectly mapped. A “direct” register is one that is mapped
directly.
V(TIP-RING) (V)
VOC
Constant
Voltage
Zone
RO=160 ΩConstant Current
Zone
ILIM ILOOP(mA)
Si3215
Rev. 0.92 25
2.2.4. Loop Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP and RING
voltages and external BJT currents. These values are
available in registers 78–89. Table 22 lists the values
that are measured and their associated registers. An
internal A/D converter samples the measured voltages
and currents from the analog sense circuitry and
translates them into the digital domain. The A/D updates
the samples at an 800 Hz rate.
Two derived values are also reported: loop voltage and
loop current. The loop voltage, VTIP –V
RING
, is reported
as a 1-bit sign, 6-bit magnitude format. For ground start
operation, the reported value is the RING voltage. The
loop current, (IQ1 – IQ2 + IQ5 –IQ6)/2, is reported in a 1-
bit sign, 6-bit magnitude format. In RING open and TIP
open states, the loop current is reported as (IQ1 – IQ2) +
(IQ5 –IQ6).
Figure 15. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)
DSP
A/D
D/AD/A
A/D
DC
Control
AC
Control
DC
Control
Loop
AC
Control
Loop
Battery Sense
Emitter Sense
DC Sense
RDC RSE RBAT
QDN
QP
QN
RE
VBAT
TIP or
RING
RBP
RAC
CAC
AC Sense
Audio
Codec Monitor A/D
SLIC DAC
On-ChipExternal Components
Σ
Si3201
Si3215
26 Rev. 0.92
Table 21. ProSLIC Linefeed Operations
LF[2:0]* Linefeed State Description
000 Open TIP and RING tri-stated.
001 Forward Active VTIP > VRING
.
010 Forward On-Hook Transmission VTIP > VRING; audio signal paths powered on.
011 TIP Open TIP tri-stated, RING active; used for ground start.
100 Ringing Ringing waveform applied to TIP and RING.
101 Reverse Active VRING > VTIP
.
110 Reverse On-Hook Transmission VRING > VTIP; audio signal paths powered on.
111 Ring Open RING tri-stated, TIP active.
*Note: The Linefeed register (LF) is located in direct Register 64.
Table 22. Measured Real Time Linefeed Interface Characteristics
Parameter Measurement
Range
Resolution Register
Bits
Location*
Loop Voltage Sense (VTIP – VRING) –94.5 to +94.5 V 1.5 V LVSP,
LVS[6:0]
Direct Register 78
Loop Current Sense –78.75 to +78.5 mA 1.25 mA LCSP,
LCS[5:0]
Direct Register 79
TIP Voltage Sense 0 to –95.88 V 0.376 V VTIP[7:0] Direct Register 80
RING Voltage Sense 0 to –95.88 V 0.376 V VRING[7:0] Direct Register 81
Battery Voltage Sense 1 (VBAT) 0 to –95.88 V 0.376 V VBATS1[7:0] Direct Register 82
Battery Voltage Sense 2 (VBAT) 0 to –95.88 V 0.376 V VBATS2[7:0] Direct Register 83
Transistor 1 Current Sense 0 to 81.35 mA 0.319 mA IQ1[7:0] Direct Register 84
Transistor 2 Current Sense 0 to 81.35 mA 0.319 mA IQ2[7:0] Direct Register 85
Transistor 3 Current Sense 0 to 9.59 mA 37.6 µA IQ3[7:0] Direct Register 86
Transistor 4 Current Sense 0 to 9.59 mA 37.6 µA IQ4[7:0] Direct Register 87
Transistor 5 Current Sense 0 to 80.58 mA 0.316 mA IQ5[7:0] Direct Register 88
Transistor 6 Current Sense 0 to 80.58 mA 0.316 mA IQ6[7:0] Direct Register 89
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly.
Si3215
Rev. 0.92 27
2.2.5. Power Monitoring and Line Fault Detection
In addition to reporting voltages and currents, the
ProSLIC continuously monitors the power dissipated in
each external bipolar transistor. Real time output power
of any one of the six linefeed transistors can be read by
setting the power monitor pointer (direct Register 76) to
point to the desired transistor and then reading the line
power output monitor (direct Register 77).
The real time power measurements are low-pass
filtered and compared to a maximum power threshold.
Maximum power thresholds and filter time constants are
software-programmable and should be set for each
transistor pair based on the characteristics of the
transistors used. Table 23 describes the registers
associated with this function. If the power in any
external transistor exceeds the programmed threshold,
a power alarm event is triggered. The ProSLIC sets the
Power Alarm register bit, generates an interrupt (if
enabled), and automatically enters the Open state (if
AOPN = 1). This feature protects the external
transistors from fault conditions and, combined with the
loop voltage and current monitors, allows diagnosis of
the type of fault condition present on the line.
The value of each thermal low-pass filter pole is set
according to the equation:
where τ is the thermal time constant of the transistor
package; 4096 is the full range of the 12-bit register, and
800 is the sample rate in Hertz. Generally, τ=3
seconds for SOT223 packages and τ= 0.16 seconds
for SOT23, but check with the manufacturer for the
package thermal constant of a specific device. For
example, the power alarm threshold and low-pass filter
values for Q5 and Q6 using a SOT223 package
transistor are computed as follows:
Thus, indirect Register 21 should be set to 150Dh.
Note: The power monitor resolution for Q3 and Q4 is different
from that of Q1, Q2, Q5, and Q6.
thermal LPF register 4096
800 τ×
------------------ 23
×=
PT56 PMAX
Resolution
------------------------------- 27
×1.28
0.0304
------------------27
×5389 150D====
Table 23. Associated Power Monitoring and Power Fault Registers
Parameter Description/
Range
Resolution Register
Bits
Location*
Power Monitor Pointer 0 to 5 points to Q1
to Q6, respectively
N/A PWRMP[2:0] Direct Register 76
Line Power Monitor Output 0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3,
Q4
30.4 mW
3.62 mW
PWROM[7:0] Direct Register 77
Power Alarm Threshold, Q1 & Q2 0 to 7.8 W 30.4 mW PPT12[7:0] Indirect Register 19
Power Alarm Threshold, Q3 & Q4 0 to 0.9 W 3.62 mW PPT34[7:0] Indirect Register 20
Power Alarm Threshold, Q5 & Q6 0 to 7.8 W 30.4 mW PPT56[7:0] Indirect Register 21
Thermal LPF Pole, Q1 & Q2 See equation above. NQ12[7:0] Indirect Register 24
Thermal LPF Pole, Q3 & Q4 See equation above. NQ34[7:0] Indirect Register 25
Thermal LPF Pole, Q5 & Q6 See equation above. NQ56[7:0] Indirect Register 26
Power Alarm Interrupt Pending Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
N/A QnAP[n+1],
where n = 1
to 6
Direct Register 19
Si3215
28 Rev. 0.92
Figure 16. Loop Closure Detection
2.2.6. Loop Closure Detection
A loop closure event signals that the terminal equipment
has gone off-hook during on-hook transmission or on-
hook active states. The ProSLIC performs loop closure
detection digitally using its on-chip monitor A/D
converter. The functional blocks required to implement
loop closure detection are shown in Figure 16. The
primary input to the system is the Loop Current Sense
value provided in the LCS register (direct Register 79).
The LCS value is processed in the Input Signal
Processor when the ProSLIC is in the on-hook
transmission or on-hook active linefeed state, as
indicated by the Linefeed Shadow register, LFS[2:0]
(direct Register 64). The data then feeds into a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The output of the low-pass filter is compared to a
programmable threshold, LCRT (indirect register 15).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has
been satisfied, the LCR bit will be set to indicate that a
valid loop closure has occurred. A loop closure interrupt
is generated if enabled by the LCIE bit (direct
Register 22). Table 24 lists the registers that must be
written or monitored to correctly detect a loop closure
condition.
2.2.7. Loop Closure Threshold Hysteresis
Programmable hysteresis to the loop closure threshold
can be enabled by setting HYSTEN = 1 (direct
Register 108, bit 0). The hysteresis is defined by LCRT
(indirect Register 15) and LCRTL (indirect Register 66),
which set the upper and lower bounds, respectively.
2.2.8. Voltage-Based Loop Closure Detection
An optional voltage-based loop closure detection mode
can be enabled by setting LCVE = 1 (direct
Register 108, bit 2). In this mode, the loop voltage is
compared to the loop closure threshold register (LCRT),
which represents a minimum voltage threshold instead
of a maximum current threshold. If hysteresis is also
enabled, LCRT represents the upper voltage boundary,
and LCRTL represents the lower voltage boundary for
hysteresis. Although voltage-based loop closure
Power Alarm Interrupt Enable Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
N/A QnAE[n+1],
where n = 1
to 6
Direct Register 22
Power Alarm
Automatic/Manual Detect
0 = manual mode
1 = enter open state
upon power alarm
N/A AOPN Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped
directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Table 23. Associated Power Monitoring and Power Fault Registers (Continued)
ISP_OUT
NCLR
LCDI
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
Debounce
Filter
+
–
LCR LCIP
LCIE
Interrupt
Logic
LCS
LVS
LCVELFS
LCRTLLCRT
HYSTEN
Si3215
Rev. 0.92 29
detection is an option, the default current-based loop
closure detection is recommended.
2.2.9. Linefeed Calibration
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL bit in direct Register 96. Upon
completion of the calibration cycle, this bit is
automatically reset.
It is recommended that a calibration be executed
following system power-up. Upon release of the chip
reset, the Si3215 will be in the open state. After
powering up the dc-dc converter and allowing it to settle
for time (tsettle) the calibration can be initiated.
Additional calibrations may be performed, but only one
calibration should be necessary as long as the system
remains powered up.
During calibration, VBAT
, VTIP
, and VRING voltages are
controlled by the calibration engine to provide the
correct external voltage conditions for the algorithm.
Calibration should be performed in the on-hook state.
RING or TIP must not be connected to ground during
the calibration.
When using the Si3201, automatic calibration routines
for RING gain mismatch and TIP gain mismatch should
not be performed. Instead of running these two
calibrations automatically, consult “AN35: Si321x User’s
Quick Reference Guide”, and follow the instructions for
manual calibration.
2.3. Battery Voltage Generation and
Switching
The Si3215 integrates a dc-dc converter controller that
dynamically regulates a single output voltage. This
mode eliminates the need to supply large external
battery voltages. Instead, it converts a single positive
input voltage into the real-time battery voltage needed
for any given state according to programmed linefeed
parameters.
For single to low channel count applications, the Si3215
proves to be an economical choice, as the dc-dc
converter eliminates the need to design and build high-
voltage power supplies.
2.3.1. DC-DC Converter General Description
The dc-dc converter dynamically generates the large
negative voltages required to operate the linefeed
interface. The Si3215 acts as the controller for a buck-
boost dc-dc converter that converts a positive dc
voltage into the desired negative battery voltage. In
addition to eliminating external power supplies, this
allows the Si3215 to dynamically control the battery
voltage to the minimum required for any given mode of
operation.
Two different dc-dc circuit options are offered: a BJT/
inductor version and a MOSFET/transformer version.
Due to the differences on the driving circuits, there are
two different versions of the Si3215. The Si3215
supports the BJT/inductor circuit option, and the
Si3215M version supports the MOSFET solution. The
only difference between the two versions is the polarity
of the DCFF pin with respect to the DCDRV pin. For the
Si3215, DCDRV and DCFF are of opposite polarity. For
the Si3215M, DCDRV and DCFF are of the same
polarity. Table 25 summarizes these differences.
Extensive design guidance on each of these circuits can
be obtained from “AN45: Design Guide for the Si3210
DC-DC Converter” and from an interactive dc-dc
converter design spreadsheet. Both of these documents
are available on the Silicon Laboratories website
(www.silabs.com).
Table 24. Register Set for Loop
Closure Detection
Parameter Register Location
Loop Closure
Interrupt Pending
LCIP Direct Reg. 19
Loop Closure
Interrupt Enable
LCIE Direct Reg. 22
Loop Closure Threshold LCRT[5:0] Indirect Reg. 15
Loop Closure
Threshold—Lower
LCRTL[5:0] Indirect Reg. 66
Loop Closure Filter
Coefficient
NCLR[12:0] Indirect Reg. 22
Loop Closure Detect
Status (monitor only)
LCR Direct Reg. 68
Loop Closure Detect
Debounce Interval
LCDI[6:0] Direct Reg. 69
Hysteresis Enable HYSTEN Direct Reg. 108
Voltage-Based Loop
Closure
LCVE Direct Reg. 108
Table 25. Si3215 and Si3215M Differences
Device DCFF Signal
Polarity
DCPOL
Si3215 = DCDRV 0
Si3215M = DCDRV 1
Notes:
1. DCFF signal polarity with respect to DCDRV signal.
2. Direct Register 93, bit 5; This is a read-only bit.
Si3215
30 Rev. 0.92
2.3.2. BJT/Inductor Circuit Option Using Si3215
The BJT/Inductor circuit option, as defined in Figure 10
on page 17, offers a flexible, low-cost solution.
Depending on selected L1 inductance value and the
switching frequency, the input voltage (VDC) can range
from 5 V to 30 V. By nature of a dc-dc converter’s
operation, peak and average input currents can become
large with small input voltages. Consider this when
selecting the appropriate input voltage and power rating
for the VDC power supply.
For this solution, a PNP power BJT (Q7) switches the
current flow through low ESR inductor L1. The Si3215
uses the DCDRV and DCFF pins to switch Q7 on and
off. DCDRV controls Q7 through NPN BJT Q8. DCFF is
ac coupled to Q7 through capacitor C10 to assist R16 in
turning off Q7. Therefore, DCFF must have opposite
polarity to DCDRV, and the Si3215 (not Si3215M) must
be used.
2.3.3. MOSFET/Transformer Circuit Option Using
Si3215M
The MOSFET/transformer circuit option, as defined in
Figure 11, offers higher power efficiencies across a
larger input voltage range. Depending on the
transformers primary inductor value and the switching
frequency, the input voltage (VDC) can range from 3.3 V
to 35 V. Therefore, it is possible to power the entire
ProSLIC solution from a single 3.3 V or 5 V power
supply. By nature of a dc-dc converter’s operation, peak
and average input currents can become large with small
input voltages. Consider this when selecting the
appropriate input voltage and power rating for the VDC
power supply (number of REN supported).
For this solution, an n-channel power MOSFET (M1)
switches the current flow through a power transformer
T1. T1 is specified in “AN45: Design Guide for the
Si3210 DC-DC Converter” and includes several taps on
the primary side to facilitate a wide range of input
voltages. The Si3215M must be used for the application
circuit depicted in Figure 11 on page 19 because the
DCFF pin is used to drive M1 directly and, therefore,
must be the same polarity as DCDRV. DCDRV is not
used in this circuit option; connecting DCFF and
DCDRV together is not recommended.
2.3.4. DC-DC Converter Architecture
The control logic for a pulse width modulated (PWM) dc-
dc converter is incorporated in the Si3215. Output pins,
DCDRV and DCFF, are used to switch a bipolar
transistor or MOSFET. The polarity of DCFF is opposite
that of DCDRV.
The dc-dc converter circuit is powered on when the
DCOF bit in the Powerdown Register (direct
Register 14, bit 4) is cleared to 0. The switching
regulator circuit within the Si3215 is a high-
performance, pulse-width modulation controller. The
control pins are driven by the PWM controller logic in
the Si3215. The regulated output voltage (VBAT) is
sensed by the SVBAT pin and used to detect whether
the output voltage is above or below an internal
reference for the desired battery voltage. The dc
monitor pins, SDCH and SDCL, monitor input current
and voltage to the dc-dc converter external circuitry. If
an overload condition is detected, the PWM controller
will turn off the switching transistor for the remainder of
a PWM period to prevent damage to external
components. It is important that the proper value of R18
be selected to ensure safe operation. Guidance is given
in AN45.
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period, the outputs of the control pins,
DCDRV and DCFF, are asserted for a time given by the
read-only PWM Pulse Width register (direct
Register 94).
The dc-dc converter must be off for some time in each
cycle to allow the inductor or transformer to transfer its
stored energy to the output capacitor, C9. This minimum
off time can be set through the dc-dc Converter
Switching Delay register, (direct Register 93). The
number of 16.384 MHz clock cycles that the controller is
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
Monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
Because the Si3215 dynamically regulates its own
battery supply voltage using the dc-dc converter
controller, the battery voltage (VBAT) is offset from the
negative-most terminal by a programmable voltage
(VOV) to allow voltage headroom for carrying audio
signals.
As mentioned previously, the Si3215 dynamically
adjusts VBAT to suit the particular circuit requirement. To
illustrate this, the behavior of VBAT in the active state is
shown in Figure 17. In the active state, the TIP-to-RING
open circuit voltage is kept at VOC in the constant
voltage region while the regulator output voltage,
VBAT =V
CM + VOC + VOV.
When the loop current attempts to exceed ILIM, the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track RLOOP
. As the TIP
terminal is kept at a constant voltage, it is the RING
Si3215
Rev. 0.92 31
terminal voltage that tracks RLOOP
, and, as a result, the
|VBAT| voltage will also track RLOOP
. In this state,
|VBAT|=I
LIM x RLOOP + VCM +VOV. As RLOOP decreases
below the VOC/ILIM mark, the regulator output voltage
can continue to track RLOOP (TRACK = 1), or the RLOOP
tracking mechanism is stopped when |VBAT|=|V
BATL|
(TRACK = 0). The former case is the more common
application and provides the maximum power
dissipation savings. In principle, the regulator output
voltage can go as low as |VBAT|=V
CM+ VOV, offering
significant power savings.
When TRACK = 0, |VBAT| will not decrease below
VBATL. The RING terminal voltage, however, continues
to decrease with decreasing RLOOP
. The power
dissipation on the NPN bipolar transistor driving the
RING terminal can become large and may require a
higher power rating device. The non-tracking mode of
operation is required by specific terminal equipment,
which, in order to initiate certain data transmission
modes, goes briefly on-hook to measure the line voltage
to determine whether there is any other off-hook
terminal equipment on the same line. TRACK = 0 mode
is desired since the regulator output voltage has long
settling time constants (on the order of tens of
milliseconds) and cannot change rapidly for TRACK = 1
mode. Therefore, the brief on-hook voltage
measurement would yield approximately the same
voltage as the off-hook line voltage and cause the
terminal equipment to incorrectly sense another off-
hook terminal.
Figure 17. VTIP
, VRING
, and VBAT in the Forward Active State
Constant I Region Constant V Region
VOC
ILIM
VCM
VOC
VOV
VOV
VRING
VBAT
VBATL
RLOOP
V
VTIP
TRACK=1
TRACK=0
|VTIP - VRING|
Si3215
32 Rev. 0.92
2.3.5. DC-DC Converter Enhancements
The Si3215 supports two enhancements to the dc-dc
converter. The first is a multi-threshold error control
algorithm that enables the dc-dc converter to adjust
more quickly to voltage changes. This option is enabled
by setting DCSU = 1 (direct Register 108, bit 5). The
second enhancement is an audio band filter that
removes audio band noise from the dc-dc converter
control loop. This option is enabled by setting DCFIL = 1
(direct Register 108, bit 1).
2.3.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the VBATH
register (direct Register 74). VBATH can be set between
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, VBATH must be set larger than the ringing
amplitude. At the end of each ringing burst, the dc-dc
converter adjusts back to active state regulation as
described above.
2.4. Tone Generation
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single- or
dual-tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip. The tones can be sent to either the
receive or transmit paths (see Figure 22 on page 40).
2.4.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 18. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 27.
Table 26. Associated Relevant DC-DC Converter Registers
Parameter Range Resolution Register Bit Location
DC-DC Converter Power-Off
Control
N/A N/A DCOF Direct Register 14
DC-DC Converter Calibration
Enable/Status
N/A N/A DCCAL Direct Register 93
DC-DC Converter PWM Period 0 to 15.564 µs 61.035 ns DCN[7:0] Direct Register 92
DC-DC Converter Min. Off Time (0 to 1.892 µs) + 4 ns 61.035 ns DCTOF[4:0] Direct Register 93
High Battery Voltage—VBATH 0 to –94.5 V 1.5 V VBATH[5:0] Direct Register 74
Low Battery Voltage—VBATL 0 to –94.5 V 1.5 V VBATL[5:0] Direct Register 75
VOV 0 to –9 V or
0 to –13.5 V
1.5 V VMIND[3:0]
VOV
Indirect Register 64
Direct Register 66
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Si3215
Rev. 0.92 33
Figure 18. Simplified Tone Generator Diagram
2.4.2. Oscillator Frequency and Amplitude
Each of the two-tone generators contains a two-pole
resonate oscillator circuit with a programmable
frequency and amplitude, which are programmed via
indirect registers OSC1, OSC1X, OSC1Y, OSC2,
OSC2X, and OSC2Y. The sample rate for the two
oscillators is 16 kHz. The equations are as follows:
coeffn=cos(2π fn/16 kHz),
where fn is the frequency to be generated;
OSCn = coeffnx(2
15);
where desired Vrms is the amplitude to be generated;
OSCnY = 0,
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, in order to generate a DTMF digit of 8, the
two required tones are 852 Hz and 1336 Hz. Assuming
the generation of half-scale values (ignoring twist) is
desired, the following values are calculated:
OSC1Y = 0
OSC2 = 0.86550 (215) = 28361 = 6EC8h
OSC2Y = 0
The computed values above would be written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the oscillators and
direct their outputs.
2.4.3. Tone Generator Cadence Programming
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OAT1 (direct
registers 36 and 37) for tone generator 1 and OAT2
(direct registers 40 and 41) for tone generator 2.
To enable automatic cadence for tone generator 1,
define the OAT1 and OIT1 registers and then set the
O1TAE bit (direct Register 32, bit 4) and O1TIE bit
(direct Register 32, bit 3). This enables each of the
timers to control the state of the Oscillator Enable bit,
O1E (direct Register 32, bit 2). The 16-bit counter will
begin counting until the active timer expires, at which
time the 16-bit counter will reset to zero and begin
OZn
OSSn
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Two-Pole
Resonance
Oscillator
16-Bit
Modulo
Counter
OATn
OITn
OITnE
OATnE
OSCn
OSCnY
OSCnX
Load
Logic
Zero
Cross
Logic Signal
Routing
OnSO
to TX Path
to RX Path
INT
Logic
OnIP
OnIE
INT
Logic
OnAP
OnAE
REL*
Register
Load
Enable
16 kHz
Clock
Zero Cross
OnE
OAT
Expire
OIT
Expire
8 kHz
Clock
OSCnX 1
4
---1 coeff–
1 coeff+
------------------------×215 1–()×Desired Vrms
1.11 Vrms
-------------------------------------
×=
coeff1
2π852
16000
-----------------
⎝⎠
⎛⎞
cos 0.94455==
OSC1 0.94455 215
()30951 78E6h===
OSC1X 1
4
---0.05545
1.94455
---------------------×215 1–()×0.5×692 2B3h===
coeff2
2π1336
16000
--------------------
⎝⎠
⎛⎞
cos 0.86550==
OSC2X 1
4
---0.13450
1.86550
---------------------×215 1–()×0.5×1098 44Bh===
Si3215
34 Rev. 0.92
counting until the inactive timer expires. The cadence
continues until the user clears the O1TAE and O1TIE
control bits. The zero crossing detect feature can be
implemented by setting the OZ1 bit (direct Register 32,
bit 5). This ensures that each oscillator pulse ends
without a dc component. The timing diagram in
Figure 19 is an example of an output cadence using the
zero crossing feature.
One-shot oscillation can be achieved by enabling O1E
and O1TAE. Direct control over the cadence can be
achieved by controlling the O1E bit (direct Register 32,
bit 2) directly if O1TAE and O1TIE are disabled.
The operation of tone generator 2 is identical to that of
tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simulta-
neously with the ringing oscillator due to resource shar-
ing within the hardware.
Continuous-phase frequency-shift keying (FSK)
waveforms may be created using tone generator 1 (not
available on tone generator 2) by setting the REL bit
(direct Register 32, bit 6), which enables reloading of
the OSC1, OSC1X, and OSC1Y registers at the
expiration of the active timer (OAT1).
Table 27. Associated Tone Generator Registers
Tone Generator 1
Parameter Description / Range Register Bits Location
Oscillator 1 Frequency Coefficient Sets oscillator frequency OSC1[15:0] Indirect Register 0
Oscillator 1 Amplitude Coefficient Sets oscillator amplitude OSC1X[15:0] Indirect Register 1
Oscillator 1 initial phase coefficient Sets initial phase OSC1Y[15:0] Indirect Register 2
Oscillator 1 Active Timer 0 to 8 seconds OAT1[15:0] Direct Registers 36 & 37
Oscillator 1 Inactive Timer 0 to 8 seconds OIT1[15:0] Direct Register 38 & 39
Oscillator 1 Control Status and control
registers
OSS1, REL, OZ1,
O1TAE, O1TIE,
O1E, O1SO[1:0]
Direct Register 32
Tone Generator 2
Parameter Description/Range Register Location
Oscillator 2 Frequency Coefficient Sets oscillator frequency OSC2[15:0] Indirect Register 3
Oscillator 2 Amplitude Coefficient Sets oscillator amplitude OSC2X[15:0] Indirect Register 4
Oscillator 2 initial phase coefficient Sets initial phase OSC2Y[15:0] Indirect Register 5
Oscillator 2 Active Timer 0 to 8 seconds OAT2[15:0] Direct Registers 40 & 41
Oscillator 2 Inactive Timer 0 to 8 seconds OIT2[15:0] Direct Register 42 & 43
Oscillator 2 Control Status and control
registers
OSS2, OZ2,
O2TAE, O2TIE,
O2E, O2SO[1:0]
Direct Register 33
Si3215
Rev. 0.92 35
Figure 19. Tone Generator Timing Diagram
2.4.4. Enhanced FSK Waveform Generation
Enhanced FSK generation capabilities can be enabled
by setting FSKEN = 1 (direct Register 108, bit 6) and
REN = 1 (direct Register 32, bit 6). In this mode, the
user can define mark (1) and space (0) attributes once
during initialization by defining indirect registers 69–74.
The user need only indicate 0-to-1 and 1-to-0 transitions
in the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift Keying (FSK) Modulation” gives detailed
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
2.4.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator 2 are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
2.5. Ringing Generation
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing, including ringing frequency,
waveform, amplitude, dc offset, and ringing cadence,
are software-programmable. Both sinusoidal and
trapezoidal ringing waveforms are supported, and the
trapezoidal crest factor is programmable. Ringing
signals of up to 88 V peak or more can be generated,
enabling the ProSLIC to drive a 5 REN (1380 Ω +
40 µF) ringer load across loop lengths of 2000 feet
(160 Ω) or more.
2.5.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoid ringing
waveform is generated using an internal two-pole
resonance oscillator circuit with programmable
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling frequencies, the ringing waveform is
generated at a 1 kHz rate instead of 8 kHz.
The ringing generator has two timers that function the
same as for the tone generator timers. They allow on/off
cadence settings up to 8 seconds on/ 8 seconds off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
Table 28 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
with the ringing generator due to resource sharing
within the hardware.
...
...
0,1 ... 0,1 ......, OAT1 ..., OAT1..., OIT10,1 ... 0,1 ...
O1E
OSS1
Tone
Gen. 1
Signal
Output
Si3215
36 Rev. 0.92
When the ringing state is invoked by writing
LF[2:0] = 100 (direct Register 64), the ProSLIC will go
into the ringing state and start the first ring. At the
expiration of RAT, the ProSLIC will turn off the ringing
waveform and go to the on-hook transmission state. At
the expiration of RIT, ringing will again be initiated. This
process will continue as long as the two timers are
enabled and the Linefeed Control register is set to the
ringing state.
2.5.2. Sinusoidal Ringing
To configure the ProSLIC for sinusoidal ringing, the
frequency and amplitude are initialized by writing to the
following indirect registers: RCO, RNGX, and RNGY.
The equations for RCO, RNGX, and RNGY are as
follows:
where
and f = desired ringing frequency in hertz.
In selecting a ringing amplitude, the peak TIP-to-RING
ringing voltage must be greater than the selected on-
hook line voltage setting (VOC, direct Register 72). For
example, to generate a 70 VPK, 20 Hz ringing signal,
the equations are as follows:
In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
Table 28. Registers for Ringing Generation
Parameter Range/ Description Register
Bits
Location
Ringing Waveform Sine/Trapezoid TSWS Direct Register 34
Ringing Voltage Offset Enable Enabled/
Disabled
RVO Direct Register 34
Ringing Active Timer Enable Enabled/
Disabled
RTAE Direct Register 34
Ringing Inactive Timer Enable Enabled/
Disabled
RTIE Direct Register 34
Ringing Oscillator Enable Enabled/
Disabled
ROE Direct Register 34
Ringing Oscillator Active Timer 0 to 8 seconds RAT[15:0] Direct Registers 48 and 49
Ringing Oscillator Inactive Timer 0 to 8 seconds RIT[15:0] Direct Registers 50 and 51
Linefeed Control (Initiates Ringing State) Ringing State = 100b LF[2:0] Direct Register 64
High Battery Voltage 0 to –94.5 V VBATH[5:0] Direct Register 74
Ringing dc voltage offset 0 to 94.5 V ROFF[15:0] Indirect Register 6
Ringing frequency 15 to 100 Hz RCO[15:0] Indirect Register 7
Ringing amplitude 0 to 94.5 V RNGX[15:0] Indirect Register 8
Ringing initial phase Sets initial phase for
sinewave and period
for
trapezoid
RNGY[15:0] Indirect Register 9
Common Mode Bias Adjust During Ringing 0 to 22.5 V VCMR[3:0] Indirect Register 27
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped
directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31).
RCO coeff 215
()×=
coeff 2πf
1000 Hz
-----------------------
⎝⎠
⎛⎞
cos=
RNGX 1
4
---1coeff–
1 coeff+
------------------------×215
×Desired VPK 0to94.5V()
96 V
------------------------------------------------------------------------
×=
RNGY 0=
coeff 2π20×
1000 Hz
-----------------------
⎝⎠
⎛⎞
0.99211=cos=
RCO 0.99211 215
()×32509 7EFDh===
RNGX 1
4
---0.00789
1.99211
---------------------×215
×70
96
------
×376 0177h===
RNGY 0=
Si3215
Rev. 0.92 37
2.5.3. Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC supports trapezoidal ringing. Figure 20
illustrates a trapezoidal ringing waveform with offset
VROFF
.
Figure 20. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
RCO is a value that is added or subtracted from the
waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 VPK, 20 Hz ringing
signal, the equations are as follows:
For a crest factor of 1.3 and a period of 0.05 seconds
(20 Hz), the rise time requirement is 0.0153 seconds.
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.5.4. Ringing DC voltage Offset
A dc offset can be added to the ac ringing waveform by
defining the offset voltage in ROFF (indirect Register 6).
The offset, VROFF
, is added to the ringing signal when
RVO is set to 1 (direct Register 34, bit 1). The value of
ROFF is calculated as follows:
2.5.5. Linefeed Considerations During Ringing
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and VBAT) to
maintain proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors will result.
To prevent this invalid operation, set the VBATH value
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The following discussion outlines
the considerations and equations that govern the
selection of the VBATH setting for a particular desired
peak ringing voltage.
First, the required amount of ringing overhead voltage,
VOVR, is calculated based on the maximum value of
current through the load, ILOAD,PK, the minimum current
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to VPK =87V, V
OVR = 7.5 V is a safe value.
However, to determine VOVR for a specific case, use the
following equations.
where:
NREN is the ringing REN load (max value = 5),
IOS is the offset current flowing in the line driver circuit
(max value = 2 mA), and
VAC,PK = amplitude of the ac ringing waveform.
It is good practice to provide a buffer of a few more
milliamperes for ILOAD,PK to account for possible line
leakages, etc. The total ILOAD,PK current should be
smaller than 80 mA.
time
VROFF
T=1/freq
tRISE
VTIP-RING
RNGY 1
2
---Period×8000×=
RNGX Desired VPK
96 V
----------------------------------- 215
()×=
RCO 2 RNGX×
tRISE 8000×
---------------------------------
=
tRISE
3
4
---T1 1
CF2
-----------
–
⎝⎠
⎛⎞
=
RNGY 20 Hz()
1
2
---1
20 Hz
----------------
×8000×200 C8h===
RNGX 71 VPK
()
71
96
------ 215
×24235 5EABh===
RCO 20 Hz,1.3 crest factor()
2 24235×
0.0153 8000×
--------------------------------------396 018Ch===
ROFF VROFF
96
------------------215
×=
ILOAD,PK
VAC,PK
RLOAD
------------------- IOS
+VAC,PK
NREN
6.9 kΩ
------------------
×IOS
+==
Si3215
38 Rev. 0.92
where β is the minimum expected current gain of
transistors Q5 and Q6.
The minimum value for VBATH is, therefore, given by the
following:
The ProSLIC is designed to create a fully balanced
ringing waveform, meaning that the TIP and RING
common mode voltage, (VTIP + VRING)/2, is fixed. This
voltage is referred to as VCM_RING and is
automatically set to the following:
VCMR is an indirect register that provides the headroom
by the ringing waveform with respect to the VBATH rail.
The value is set as a 4-bit setting in indirect Register 27
with an LSB voltage of 1.5 V/LSB. Register 27 should
be set with the calculated VOVR to provide voltage
headroom during ringing.
The ProSLIC has a mode to briefly increase the
maximum differential current limit between the voltage
transition of TIP and RING from ringing to a dc linefeed
state. This mode is enabled by setting ILIMEN = 1
(direct Register 108, bit 7).
2.5.6. Ring Trip Detection
A ring trip event signals that the terminal equipment has
gone off-hook during the ringing state. The ProSLIC
performs ring trip detection digitally using its on-chip
A/D converter. The functional blocks required to
implement ring trip detection are shown in Figure 21.
The primary input to the system is the loop current
sense (LCS) value provided by the current monitoring
circuitry and reported in direct Register 79. LCS data is
processed by the input signal processor when the
ProSLIC is in the ringing state as indicated by the
Linefeed Shadow register (direct Register 64). The data
then feeds into a programmable digital low-pass filter,
which removes unwanted ac signal components before
threshold detection.
The output of the low-pass filter is compared to a
programmable threshold, RPTP (indirect Register 16).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the ring trip debounce interval,
RTDI[6:0] (direct Register 70). If the debounce interval
has been satisfied, the RTP bit of direct Register 68 will
be set to indicate that a valid ring trip has occurred. A
ring trip interrupt is generated if enabled by the RTIE bit
(direct Register 22). Table 29 lists the registers that
must be written or monitored to correctly detect a ring
trip condition.
The recommended values for RPTP, NRTP, and RTDI
vary according to the programmed ringing frequency.
Register values for various ringing frequencies are
given in Table 30.
Figure 21. Ring Trip Detector
VOVR ILOAD,PK
β1+
β
-------------
×80.6 Ω1V+()×=
VBATH VAC,PK VROFF VOVR
++=
VCM_RING VBATH VCMR–
2
----------------------------------------------
=
LCS ISP_OUT
LFS
NRTP
RPTP
RTDI
Input
Signal
Processor
Digital
LPF
Ring Trip
Threshold
Debounce
Filter
+
–
RTP RTIP
RTIE
Interrupt
Logic
DBIRAW
Si3215
Rev. 0.92 39
2.6. Audio Path
Unlike traditional SLICs, the codec function is integrated
into the ProSLIC. The 16-bit codec offers programmable
gain/attenuation blocks and several loop-back modes.
The signal path block diagram is shown in Figure 22.
2.6.1. Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is amplified by the
analog transmit amplifier, ATX, prior to the A/D
converter. The gain of the ATX is user-selectable to one
of mute/–3.5/0/3.5 dB options. The main role of ATX is
to coarsely adjust the signal swing to be as close as
possible to the full-scale input of the A/D converter in
order to maximize the signal-to-noise ratio of the
transmit path. After passing through an anti-aliasing
filter, the analog signal is processed by the A/D
converter, producing an 8 kHz, 16-bit wide, linear PCM
data stream. The standard requirements for transmit
path attenuation for signals above 3.4 kHz are
implemented as part of the combined decimation filter
characteristic of the A/D converter. One more digital
filter is available in the transmit path, THPF. THPF
implements the high-pass attenuation requirements for
signals below 65 Hz. The linear PCM data stream
output from THPF is amplified by the transmit-path
programmable gain amplifier, ADCG, which can be
programmed from –∞dB to 6 dB. The final step in the
transmit path signal processing is the user-selectable
A-law or µ-law compression, which can reduce the data
stream word width to 8 bits. Depending on the
PCM_Mode register selection, every 8-bit compressed
serial data word will occupy one time slot on the PCM
highway, or every 16-bit uncompressed serial data
word will occupy two time slots on the PCM highway.
Table 29. Associated Registers for Ring Trip Detection
Parameter Register Location
Ring Trip Interrupt Pending RTIP Direct Register 19
Ring Trip Interrupt Enable RTIE Direct Register 22
Ring Trip Detect Debounce Interval RTDI[6:0] Direct Register 70
Ring Trip Threshold RPTP[5:0] Indirect Register 16
Ring Trip Filter Coefficient NRTP[12:0] Indirect Register 23
Ring Trip Detect Status (monitor only) RTP Direct Register 68
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Table 30. Recommended Ring Trip Values for Ringing
Ringing Frequency NRTP RPTP RTDI
Hz decimal hex decimal hex decimal hex
16.667 64 0200 34 mA 3600 15.4 ms 0F
20 100 0320 34 mA 3600 12.3 ms 0B
30 112 0380 34 mA 3600 8.96 ms 09
40 128 0400 34 mA 3600 7.5 ms 07
50 213 06A8 34 mA 3600 5 ms 05
60 256 0800 34 mA 3600 4.8 ms 05
Si3215
40 Rev. 0.92
+
Mute
H
From Billing Tone
DAC
From Billing
Tone DAC
ATX
+
Interpolation
Filter Mute
DACG
µ/A-law
Compressor
µ/A-law
Expander
Serial
Input
Decimation
Filter
RHPF
THPF Serial
Output
Digital
RX
Digital
TX
Dual Tone
Generator
Full
Analog
Loopback
ADCG
D/A
+
A/D
HYBA
H
TXM
Digital
Loopback
DLM
ALM1
Analog
Loopback
ALM2
Off Chip On Chip HYBP
Transmit Path
TIP
RING
XAC
RACGm
Ibuf
–
+
ARX
RXM
–
Figure 22. AC Signal Path Block Diagram
Si3215
Rev. 0.92 41
2.6.2. Receive Path
In the receive path, the optionally-compressed 8-bit
data is first expanded to 16-bit words. The PCMF
register bit can bypass the expansion process, in
which case two 8-bit words are assembled into one 16-
bit word. DACG is the receive path programmable gain
amplifier, which can be programmed from –∞dB to
6 dB. An 8 kHz, 16-bit signal is then provided to a D/A
converter. The resulting analog signal is amplified by
the analog receive amplifier, ARX, which is user-
selectable to one of mute/–3.5/0/3.5 dB options. It is
then applied at the input of the transconductance
amplifier (Gm), which drives the off-chip current buffer
(IBUF).
2.6.3. Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 1 on page 7 specifies the minimum
signal-to-noise-and-distortion ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both the µ-law and the A-law speech encoding allow the
audio codec to transfer and process audio signals larger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The ProSLIC overload clipping limits are
driven by the PCM encoding process. Figure 2 on page
7 shows the acceptable limits for the analog-to-analog
fundamental power transfer-function, which bounds the
behavior of ProSLIC.
The transmit path gain distortion versus frequency is
shown in Figure 3 on page 8. The same figure also
presents the minimum required attenuation for any out-
of-band analog signal that may be applied on the line.
Note the presence of a high-pass filter transfer-function,
which ensures at least 30 dB of attenuation for signals
below 65 Hz. The low-pass filter transfer function that
attenuates signals above 3.4 kHz has to exceed the
requirements specified by the equations in Figure 3 on
page 8, and it is implemented as part of the A-to-D
converter.
The receive path transfer function requirement, shown
in Figure 4 on page 9, is very similar to the transmit path
transfer function. The most notable difference is the
absence of the high-pass filter portion. The only other
differences are the maximum 2 dB attenuation at
200 Hz (as opposed to 3 dB for the transmit path) and
the 28 dB of attenuation for any frequency above
4.6 kHz. The PCM data rate is 8 kHz and, thus, no
frequencies greater than 4 kHz can be digitally encoded
in the data stream. From this point of view, at
frequencies greater than 4 kHz, the plot in Figure 4
should be interpreted as the maximum allowable
magnitude of any spurious signals that are generated
when a PCM data stream representing a sine wave
signal in the range of 300 Hz to 3.4 kHz at a level of
0 dBm0 is applied at the digital input.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 5 on page 10.
The reference in Figure 5 on page 10 is the smallest
group delay for a sine wave in the range of 500 Hz to
2500 Hz at 0 dBm0.
The block diagram for the voice-band signal processing
paths are shown in Figure 22. Both the receive and the
transmit paths employ the optimal combination of
analog and digital signal processing to provide the
maximum performance while, at the same time, offering
sufficient flexibility to allow users to optimize for their
particular application of the ProSLIC. All programmable
signal-processing blocks are symbolically indicated in
Figure 22 by a dashed arrow across them. The two-wire
(TIP/RING) voice-band interface to the ProSLIC is
implemented using a small number of external
components. The receive path interface consists of a
unity-gain current buffer, IBUF
, while the transmit path
interface is simply an ac coupling capacitor. Signal
paths, although implemented differentially, are shown
as single-ended for simplicity.
2.6.4. Transhybrid Balance
The ProSLIC provides programmable transhybrid
balance with gain block H. (See Figure 22.) In the ideal
case where the synthesized SLIC impedance matches
exactly the subscriber loop impedance, the transhybrid
balance should be set to subtract a –6 dB level from the
transmit path signal. The transhybrid balance gain can
be adjusted from –2.77 dB to +4.08 dB around the ideal
setting of –6 dB by programming the HYBA[2:0] bits of
the Hybrid Control register (direct Register 11). Note
that adjusting any of the analog or digital gain blocks will
not require any modification of the transhybrid balance
gain block, as the transhybrid gain is subtracted from
the transmit path signal prior to any gain adjustment
stages. The transhybrid balance can also be disabled, if
desired, using the appropriate register setting.
2.6.5. Loopback Testing
Four loopback test options are available in the ProSLIC:
The full analog loopback (ALM2) tests almost all the
circuitry of both the transmit and receive paths. The
compressed 8-bit word transmit data stream is fed
back serially to the input of the receive path
expander. (See Figure 22.) The signal path starts
with the analog signal at the input of the transmit
path and ends with an analog signal at the output of
Si3215
42 Rev. 0.92
the receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 22.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows the testing of the analog
signal processing circuitry of the Si3215 completely
independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path is fed back to
the input of the transmit path by way of the hybrid
filter path. (See Figure 22.) The signal path starts
with 8-bit PCM data input to the receive path and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and interface directly to the 16-bit data.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3215 completely
independently of any analog signal processing
activity. The user can bypass the companding
process and interface directly to the 16-bit data.
2.7. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600 Ω will be loaded into the TISS
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC) a
switched capacitor network (XAC) and a
transconductance amplifier (Gm). (See Figure 22.) RAC
creates the real portion and XAC creates the imaginary
portion of Gm’s input. Gm then creates a current that
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer (IBUF), which is implemented using
transistor Q1 and Q2 (see Figure on page 20). Gm is
referenced to an off-chip resistor (R15).
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
The Si3215 supports the option to remove the internal
reference resistor used to synthesize ac impedances for
600 + 1 µF and 900 + 2.16 µF settings so that an
external resistor reference may be used. This option is
enabled by setting ZSEXT = 1 (direct Register 108,
bit 4). When 600 + 1 µF or 900 + 2.16 µF impedances
are selected, an internal reference resistor is removed
from the impedance synthesis circuit to accommodate
an external resistor, RZREF
, which is inserted into the
application circuit as shown in Figure 23.
Figure 23. RZREF External Resistor Placement
2.8. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz, or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined via a counter clocked by PCLK. The
three-bit ratio information is automatically transferred
into an internal register, PLL_MULT, following a reset of
the ProSLIC. The PLL_MULT is used to control the
internal PLL, which multiplies PCLK as needed to
generate 16.384 MHz rate needed to run the internal
filters and other circuitry.
The PLL clock synthesizer settles very quickly following
powerup. However, the settling time depends on the
PCLK frequency, and it can be approximately predicted
by the following equation:
to TIP
to RING
Si3215
STIPAC
SRINGAC
RZREF
C3
C4
R8
R9
For 600 + 1 µF, RZREF = 12 kΩ and C3, C4 = 100 nF.
For 900 + 2.16 µF, RZREF = 12 kΩ and C3, C4 = 220 nF.
TSETTLE
64
FPCLK
-----------------
=
Si3215
Rev. 0.92 43
2.9. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Loop current/ring ground detected
Ring trip detected
Power alarm
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
Indirect register access complete
The interface to the interrupt logic consists of six
registers. Three interrupt status registers contain one bit
for each of the above interrupt functions. These bits will
be set when an interrupt is pending for the associated
resource. Three interrupt enable registers also contain
one bit for each interrupt function. In the case of the
interrupt enable registers, the bits are active high. Refer
to the appropriate functional description section for
operational details of the interrupt functions.
When a resource reaches an interrupt condition, it will
signal an interrupt to the interrupt control block. The
interrupt control block will then set the associated bit in
the interrupt status register if the enable bit for that
interrupt is set. The INT pin is a NOR of the bits of the
interrupt status registers. Therefore, if a bit in the
interrupt status registers is asserted, IRQ will assert low.
Upon receiving the interrupt, the interrupt handler
should read interrupt status registers to determine
which resource is requesting service. To clear a pending
interrupt, write the desired bit in the appropriate
interrupt status register to 1. Writing a 0 has no effect.
This provides a mechanism for clearing individual bits
when multiple interrupts occur simultaneously. While the
interrupt status registers are non-zero, the INT pin will
remain asserted.
2.10. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface
modeled after commonly-available microcontroller and
serial peripheral devices. The interface consists of a
clock (SCLK), chip select (CS), serial data input (SDI),
and serial data output (SDO). Data is transferred a byte
at a time with each register access consisting of a pair
of byte transfers. Figures 24 and 25 illustrate read and
write operation in the SPI bus.
The first byte of the pair is the command/address byte.
The MSB of this byte indicates a register read when 1
and a register write when 0. The remaining seven bits of
the command/address byte indicate the address of the
register to be accessed. The second byte of the pair is
the data byte. Because the falling edge of CS provides
resynchronization of the SPI state machine in the event
of a framing error, it is recommended (but not required)
that CS be taken high between byte transfers as shown
in Figures 24 and 25. During a read operation, the SDO
becomes active, and the 8-bit contents of the register
are driven out MSB first. The SDO will be high
impedence on either the falling edge of SCLK following
the LSB or the rising of CS as specified by the SPIM bit
(direct Register 0, bit 6). SDI is a “don’t care” during the
data portion of read operations. During write operations,
data is driven into the ProSLIC via the SDI pin MSB first.
The SDO pin will remain high impedance during write
operations. Data always transitions with the falling edge
of the clock and is latched on the rising edge. The clock
should return to a logic high when no transfer is in
progress.
Indirect registers are accessed through direct registers
29 through 30. Instructions on how to access them are
presented in “3.Control Registers” beginning on page
50.
There are a number of variations of usage on this four-
wire interface:
Continuous clocking. During continuous clocking,
the data transfers are controlled by the assertion of
the CS pin. CS must assert before the falling edge of
SCLK on which the first bit of data is expected during
a read cycle, and must remain low for the duration of
the 8-‘bit transfer (command/address or data).
SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tristating its output during the
data byte transfer of a read operation.
Daisy chain mode. This mode allows
communication with banks of up to eight ProSLIC
devices using one chip select signal. When the
SPIDC bit in the SPI Mode Select register is set,
data transfer mode changes to a 3-byte operation: a
chip select byte, an address/control byte, and a data
byte. Using the circuit shown in Figure 26, a single
device may select from the bank of devices by
setting the appropriate chip select bit to 1. Each
device uses the LSB of the chip select byte, shifts
the data right by one bit, and passes the chip select
byte using the SDITHRU pin to the next device in the
chain. Address/control and data bytes are unaltered.
Si3215
44 Rev. 0.92
Figure 24. Serial Write 8-Bit Mode
Figure 25. Serial Read 8-Bit Mode
SCLK
CS
SDI
SDO
High Impedance
0a0a1a2a3a4a5a6 d7 d0d1d2d3d4d5d6
Don't
Care
SCLK
CS
SDI
SDO
1a0a1a2a3a4a5a6
d7 d0d1d2d3d4d5d6
Don't Care
High Impedance
Don't
Care
Si3215
Rev. 0.92 45
Figure 26. SPI Daisy Chain Mode
CPU
SDO
CS
SDI
CS SDI
SDITHRU
SDO
CS SDI
SDITHRU
SDO
C7 C6 C5 C4 C3 C2 C1 C0 R/W A6 A5 A4 A3 A2 A1 A0
– C7 C6 C5 C4 C3 C2 C1
– – C7 C6 C5 C4 C3 C2
Chip Select Byte Address Byte Data Byte
SCLK
SDI0
SDI1
SDI2
SDI3
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0– – – C7 C6 C5 C4 C3
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the
LSB of the chip select byte for its chip select.
CS SDI
SDITHRU
SDO
CS SDI
SDITHRU
SDO
SDI0
SDI3
SDI2
SDI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Si3215
46 Rev. 0.92
2.11. PCM Interface
The ProSLIC contains a flexible programmable interface
for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK
and FSYNC inputs as well as the PCM Mode Select
(direct Register 1), PCM Transmit Start Count (direct
registers 2 and 3), and PCM Receive Start Count (direct
registers 4 and 5) registers. The interface can be
configured to support from 4 to 128 8-bit timeslots in
each frame. This corresponds to PCLK frequencies of
256 kHz to 8.192 MHz in power-of-2 increments.
(768 kHz and 1.536 MHz are also available.) Timeslots
for data transmission and reception are independently
configured using the TXS and RXS registers. By setting
the correct starting point of the data, the ProSLIC can
be configured to support long FSYNC and short FSYNC
variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel
time slots. DTX data is high-impedance except for the
duration of the 8-bit PCM transmit. DTX will return to
high impedance either on the negative edge of PCLK
during the LSB or on the positive edge of PCLK
following the LSB. This is based on the setting of the
TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of data by
multiple sources in adjacent timeslots without the risk of
driver contention. In addition to 8-bit data modes, there
is a 16-bit mode provided. This mode can be activated
via the PCMT bit of the PCM Mode Select register. GCI
timing is also supported in which the duration of a data
bit is two PCLK cycles. This mode is also activated via
the PCM Mode Select register. Setting the TXS or RXS
register greater than the number of PCLK cycles in a
sample period will stop data transmission because TXS
or RXS will never equal the PCLK count. Figures 27–30
illustrate the usage of the PCM highway interface to
adapt to common PCM standards.
Figure 27. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 28. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3215
Rev. 0.92 47
Figure 29. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
Figure 30. GCI Example, Timeslot 1 (TXS/RXS = 0)
2.12. Companding
The ProSLIC supports both µ-255 Law and A-Law companding formats in addition to linear data. These 8-bit
companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. µ-255
Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is
selected via the PCMF register. Tables 31 and 32 define the µ-Law and A-Law encoding formats.
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3215
48 Rev. 0.92
Table 31. µ-Law Encode-Decode Characteristics1,2
Segment
Number
#Intervals X Interval Size Value at Segment Endpoints Digital Code Decode Level
8 16 X 256
8159
.
.
.
4319
4063
10000000b
10001111b
8031
4191
7 16 X 128
.
.
.
2143
2015 10011111b 2079
6 16 X 64
.
.
.
1055
991 10101111b 1023
5 16 X 32
.
.
.
511
479 10111111b 495
4 16 X 16
.
.
.
239
223 11001111b 231
3 16 X 8
.
.
.
103
95 11011111b 99
2 16 X 4
.
.
.
35
31 11101111b 33
1 15 X 2
__________________
1 X 1
.
.
.
3
1
0
11111110b
11111111b
2
0
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
Si3215
Rev. 0.92 49
Table 32. A-Law Encode-Decode Characteristics1,2
Segment
Number
#intervals X interval size Value at segment endpoints Digital Code Decode Level
716 X 128
4096
3968
.
.
2176
2048
10101010b
10100101b
4032
2112
616 X 64
.
.
.
1088
1024 10110101b 1056
516 X 32
.
.
.
544
512 10000101b 528
416 X 16
.
.
.
272
256 10010101b 264
3 16 X 8
.
.
.
136
128 11100101b 132
2 16 X 4
.
.
.
68
64 11110101b 66
1
32 X 2
.
.
.
2
0 11010101b 1
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.
2. Digital code includes inversion of all even numbered bits.
Si3215
50 Rev. 0.92
3. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 33. Direct Register Summary
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Setup
0 SPI Mode Select SPIDC SPIM PNI[1:0] RNI[3:0]
1 PCM Mode Select PNI2 PCME PCMF[1:0] PCMT GCI TRI
2 PCM Transmit Start
Count—Low Byte
TXS[7:0]
3 PCM Transmit Start
Count—High Byte
TXS[9:8]
4 PCM Receive Start
Count—Low Byte
RXS[7:0]
5 PCM Receive Start
Count—High Byte
RXS[9:8]
6 Part Number Identification PNI[2:0]
Audio
8 Audio Path Loopback
Control
ALM2 DLM ALM1
9 Audio Gain Control RXHP TXHP TXM RXM ATX[1:0] ARX[1:0]
10 Two-Wire Impedance
Synthesis Control
CLC[1:0] TISE TISS[2:0]
11 Hybrid Control HYBP[2:0] HYBA[2:0]
Powerdown
14 Powerdown Control 1 DCOF PFR BIASOF SLICOF
15 Powerdown Control 2 ADCM ADCON DACM DACON GMM GMON
Interrupts
18 Interrupt Status 1 RGIP RGAP O2IP O2AP O1IP O1AP
19 Interrupt Status 2 Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP
20 Interrupt Status 3 INDP
21 Interrupt Enable 1 RGIE RGAE O2IE O2AE O1IE O1AE
22 Interrupt Enable 2 Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE
23 Interrupt Enable 3 INDE
Indirect Register Access
28 Indirect Data Access—
Low Byte
IDA[7:0]
29 Indirect Data Access—
High Byte
IDA[15:8]
30 Indirect Address IAA[7:0]
Si3215
Rev. 0.92 51
31 Indirect Address Status IAS
Oscillators
32 Oscillator 1 Control OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0]
33 Oscillator 2 Control OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0]
34 Ringing Oscillator
Control
RSS RDAC RTAE RTIE ROE RVO TSWS
36 Oscillator 1 Active
Timer—Low Byte
OAT1[7:0]
37 Oscillator 1 Active
Timer—High Byte
OAT1[15:8]
38 Oscillator 1 Inactive
Timer—Low Byte
OIT1[7:0]
39 Oscillator 1 Inactive
Timer—High Byte
OIT1[15:8]
40 Oscillator 2 Active
Timer—Low Byte
OAT2[7:0]
41 Oscillator 2 Active
Timer—High Byte
OAT2[15:8]
42 Oscillator 2 Inactive
Timer—Low Byte
OIT2[7:0]
43 Oscillator 2 Inactive
Timer—High Byte
OIT2[15:8]
48 Ringing Oscillator
Active Timer—Low Byte
RAT[7:0]
49 Ringing Oscillator
Active Timer—High Byte
RAT[15:8]
50 Ringing Oscillator Inac-
tive Timer—Low Byte
RIT[7:0]
51 Ringing Oscillator Inac-
tive Timer—High Byte
RIT[15:8]
52 FSK Data FSKDAT
SLIC
63 Loop Closure Debounce
Interval for Automatic
Ringing
LCD[7:0]
64 Linefeed Control LFS[2:0] LF[2:0]
65 External Bipolar
Transistor Control
SQH CBY ETBE ETBO[1:0] ETBA[1:0]
66 Battery Feed Control VOV FVBAT TRACK
67 Automatic/Manual
Control
MNCM MNDIF SPDS AORD AOLD AOPN
Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Si3215
52 Rev. 0.92
68 Loop Closure/Ring Trip
Detect Status
DBIRAW RTP LCR
69 Loop Closure Debounce
Interval
LCDI[6:0]
70 Ring Trip Detect
Debounce Interval
RTDI[6:0]
71 Loop Current Limit ILIM[2:0]
72 On-Hook Line Voltage VSGN VOC[5:0]
73 Common Mode Voltage VCM[5:0]
74 High Battery Voltage VBATH[5:0]
75 Low Battery Voltage VBATL[5:0]
76 Power Monitor Pointer PWRMP[2:0]
77 Line Power Output
Monitor
PWROM[7:0]
78 Loop Voltage Sense LVSP LVS[5:0]
79 Loop Current Sense LCSP LCS[5:0]
80 TIP Voltage Sense VTIP[7:0]
81 RING Voltage Sense VRING[7:0]
82 Battery Voltage Sense 1 VBATS1[7:0]
83 Battery Voltage Sense 2 VBATS2[7:0]
84 Transistor 1 Current
Sense
IQ1[7:0]
85 Transistor 2 Current
Sense
IQ2[7:0]
86 Transistor 3 Current
Sense
IQ3[7:0]
87 Transistor 4 Current
Sense
IQ4[7:0]
88 Transistor 5 Current
Sense
IQ5[7:0]
89 Transistor 6 Current
Sense
IQ6[7:0]
92 DC-DC Converter PWM
Period
DCN[7:0]
93 DC-DC Converter Switch-
ing Delay
DCCAL DCPOL DCTOF[4:0]
94 PWM Pulse Width DCPW[7:0]
95 Reserved
Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Si3215
Rev. 0.92 53
96 Calibration Control/
Status Register 1
CAL CALSP CALR CALT CALD CALC CALIL
97 Calibration Control/
Status Register 2
CALM1 CALM2 CALDAC CALADC CALCM
98 RING Gain Mismatch Cal-
ibration Result
CALGMR[4:0]
99 TIP Gain Mismatch
Calibration Result
CALGMT[4:0]
100 Differential Loop
Current Gain
Calibration Result
CALGD[4:0]
101 Common Mode Loop Cur-
rent Gain
Calibration Result
CALGC[4:0]
102 Current Limit
Calibration Result
CALGIL[3:0]
103 Monitor ADC Offset
Calibration Result
CALMG1[3:0] CALMG2[3:0]
104 Analog DAC/ADC Offset DACP DACN ADCP ADCN
105 DAC Offset Calibration
Result
DACOF[7:0]
107 DC Peak Current Monitor
Calibration Result
CMDCPK[3:0]
108 Enhancement Enable ILIMEN FSKEN DCSU LCVE DCFIL HYSTEN
Table 33. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Si3215
54 Rev. 0.92
Reset settings = 00xx_xxxx
Register 0. SPI Mode Select
BitD7D6D5D4D3D2D1D0
Name SPIDC SPIM PNI[1:0] RNI[3:0]
Type R/W R/W R R
Bit Name Function
7SPIDCSPI Daisy Chain Mode Enable.
0 = Disable SPI daisy chain mode.
1 = Enable SPI daisy chain mode.
6 SPIM SPI Mode.
0 = Causes SDO to tri-state on rising edge of SCLK of LSB.
1 = Normal operation; SDO tri-states on rising edge of CS.
5:4 PNI[1:0] Part Number Identification.
00 = Si3215
01 = Unused
10 = Unused
11 = Si3215M
3:0 RNI[3:0] Revision Number Identification.
0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc.
Si3215
Rev. 0.92 55
Reset settings = 1000_1000
Reset settings = 0000_0000
Register 1. PCM Mode Select
BitD7D6D5D4D3D2D1D0
Name PNI2 PCME PCMF[1:0] PCMT GCI TRI
Type R R/W R/W R/W R/W R/W
Bit Name Function
7PNI2Part Number Identification 2.
0 = Si3210 family
1 = Si3215 family
6 Reserved Read returns zero.
5PCME
PCM Enable.
0 = Disable PCM transfers.
1 = Enable PCM transfers.
4:3 PCMF[1:0] PCM Format.
00 = A-Law
01 = µ-Law
10 = Reserved
11 = Linear
2PCMT
PCM Transfer Size.
0 = 8-bit transfer.
1 = 16-bit transfer.
1GCI
GCI Clock Format.
0 = 1 PCLK per data bit.
1 = 2 PCLKs per data bit.
0TRI
Tri-state Bit 0.
0 = Tri-state bit 0 on positive edge of PCLK.
1 = Tri-state bit 0 on negative edge of PCLK.
Register 2. PCM Transmit Start Count—Low Byte
BitD7D6D5D4D3D2D1D0
Name TXS[7:0]
Type R/W
Bit Name Function
7:0 TXS[7:0] PCM Transmit Start Count.
PCM transmit start count equals the number of PCLKs following FSYNC before data trans-
mission begins. See Figure 27 on page 46.
Si3215
56 Rev. 0.92
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 3. PCM Transmit Start Count—High Byte
BitD7D6D5D4D3D2D1D0
Name TXS[9:8]
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1:0 TXS[9:8] PCM Transmit Start Count.
PCM transmit start count equals the number of PCLKs following FSYNC before data
transmission begins. See Figure 27 on page 46.
Register 4. PCM Receive Start Count—Low Byte
BitD7D6D5D4D3D2D1D0
Name RXS[7:0]
Type R/W
Bit Name Function
7:0 RXS[7:0] PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 27 on page 46.
Register 5. PCM Receive Start Count—High Byte
BitD7D6D5D4D3D2D1D0
Name RXS[9:8]
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1:0 RXS[9:8] PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 27 on page 46.
Si3215
Rev. 0.92 57
Reset settings = 0xx0_0000
Reset settings = 0000_0010
Register 6. Part Number Identification
BitD7D6D5D4D3D2D1D0
Name PNI[2:0]
Type R
Bit Name Function
7:5 PNI[2:0] Part Number Identification.
Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0.
000 = Si3215 100 = Reserved
001 = Reserved 101 = Reserved
010 = Reserved 110 = Reserved
011 = Si3215M 111 = Reserved
4:0 Reserved Read returns zero.
Register 8. Audio Path Loopback Control
BitD7D6D5D4D3D2D1D0
Name ALM2 DLM ALM1
Type R/W R/W R/W
Bit Name Function
7:3 Reserved Read returns zero.
2ALM2
Analog Loopback Mode 2. (See Figure 22 on page 40.)
0 = Full analog loopback mode disabled.
1 = Full analog loopback mode enabled.
1DLM
Digital Loopback Mode. (See Figure 22 on page 40.)
0 = Digital loopback disabled.
1 = Digital loopback enabled.
0ALM1
Analog Loopback Mode 1. (See Figure 22 on page 40.)
0 = Analog loopback disabled.
1 = Analog loopback enabled.
Si3215
58 Rev. 0.92
Reset settings = 0000_0000
Register 9. Audio Gain Control
BitD7D6D5D4D3D2D1D0
Name RXHP TXHP TXM RXM ATX[1:0] ARX[1:0]
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7RXHPReceive Path High Pass Filter Disable.
0 = HPF enabled in receive path, RHDF.
1 = HPF bypassed in receive path, RHDF.
6TXHP
Transmit Path High Pass Filter Disable.
0 = HPF enabled in transmit path, THPF.
1 = HPF bypassed in transmit path, THPF.
5TXM
Transmit Path Mute.
Refer to position of digital mute in Figure 22 on page 40.
0 = Transmit signal passed.
1 = Transmit signal muted.
4RXM
Receive Path Mute.
Refer to position of digital mute in Figure 22 on page 40.
0 = Receive signal passed.
1 = Receive signal muted.
3:2 ATX[1:0] Analog Transmit Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = ATX gain = 0 dB; analog transmit path muted.
1:0 ARX[1:0] Analog Receive Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = Analog receive path muted.
Si3215
Rev. 0.92 59
Reset settings = 0000_1000
Register 10. Two-Wire Impedance Synthesis Control
BitD7D6D5D4D3D2D1D0
Name CLC[1:0] TISE TISS[2:0]
Type R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:4 CLC[1:0] Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0 TISS[2:0] Two-Wire Impedance Synthesis Selection.
000 = 600 Ω
001 = 900 Ω
010 = Japan (600 Ω + 1 µF); requires external resistor RZREF =12kΩ and C3, C4 = 100 nF.
011 = 900 Ω + 2.16 µF; requires external resistor RZREF =18kΩ and C3, C4 = 220 nF.
100 = CTR21 270 Ω + (750 Ω || 150 nF)
101 = Australia/New Zealand 220 Ω + (820 Ω || 120 nF)
110 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF)
111 = China 200 Ω + (680 Ω || 100 nF)
Si3215
60 Rev. 0.92
Reset settings = 0011_0011
Register 11. Hybrid Control
BitD7D6D5D4D3D2D1D0
Name HYBP[2:0] HYBA[2:0]
Type R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011=0dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
3 Reserved Read returns zero.
2:0 HYBA[2:0] Audio Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011=0dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
Si3215
Rev. 0.92 61
Reset settings = 0001_0000
Register 14. Powerdown Control 1
BitD7D6D5D4D3D2D1D0
Name DCOF PFR BIASOF SLICOF
Type R/W R/W R/W R/W
Bit Name Function
7:5 Reserved Read returns zero.
4 DCOF DC-DC Converter Power-Off Control
0 = Automatic power control.
1 = Override automatic control and force dc-dc circuitry off.
3PFR
PLL Free-Run Control.
0 = Automatic free-run control.
1 = Override automatic control and force PLL into free-run state.
2 Reserved Read returns zero.
1 BIASOF DC Bias Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force dc bias circuitry off.
0SLICOF
SLIC Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force SLIC circuitry off.
Si3215
62 Rev. 0.92
Reset settings = 0000_0000
Register 15. Powerdown Control 2
BitD7D6D5D4D3D2D1D0
Name ADCM ADCON DACM DACON GMM GMON
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5 ADCM Analog to Digital Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; ADCON controls on/off state.
4ADCON
Analog to Digital Converter On/Off Power Control.
When ADCM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
ADCON has no effect when ADCM = 0.
3DACM
Digital to Analog Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; DACON controls on/off state.
2DACON
Digital to Analog Converter On/Off Power Control.
When DACM = 1:
0 = Digital to analog converter powered off.
1 = Digital to analog converter powered on.
DACON has no effect when DACM = 0.
1GMM
Transconductance Amplifier Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; GMON controls on/off state.
0GMON
Transconductance Amplifier On/Off Power Control.
When GMM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
GMON has no effect when GMM = 0.
Si3215
Rev. 0.92 63
Reset settings = 0000_0000
Register 18. Interrupt Status 1
BitD7D6D5D4D3D2D1D0
Name RGIP RGAP O2IP O2AP O1IP O1AP
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5RGIP
Ringing Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
4RGAP
Ringing Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
3O2IP
Oscillator 2 Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
2O2AP
Oscillator 2 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
1O1IP
Oscillator 1 Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0O1AP
Oscillator 1 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Si3215
64 Rev. 0.92
Reset settings = 0000_0000
Register 19. Interrupt Status 2
BitD7D6D5D4D3D2D1D0
Name Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7Q6APPower Alarm Q6 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
6Q5AP
Power Alarm Q5 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
5Q4AP
Power Alarm Q4 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
4Q3AP
Power Alarm Q3 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
3Q2AP
Power Alarm Q2 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
2Q1AP
Power Alarm Q1 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
1LCIP
Loop Closure Transition Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0RTIP
Ring Trip Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Si3215
Rev. 0.92 65
Reset settings = 0000_0000
Register 20. Interrupt Status 3
BitD7D6D5D4D3D2D1D0
Name INDP
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1INDP
Indirect Register Access Serviced Interrupt.
This bit is set once a pending indirect register service request has been completed. Writ-
ing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0 Reserved Read returns zero.
Si3215
66 Rev. 0.92
Reset settings = 0000_0000
Register 21. Interrupt Enable 1
BitD7D6D5D4D3D2D1D0
Name RGIE RGAE O2IE O2AE O1IE O1AE
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5RGIE
Ringing Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
4RGAE
Ringing Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
3O2IE
Oscillator 2 Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
2O2AE
Oscillator 2 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1O1IE
Oscillator 1 Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0O1AE
Oscillator 1 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Si3215
Rev. 0.92 67
Reset settings = 0000_0000
Register 22. Interrupt Enable 2
BitD7D6D5D4D3D2D1D0
Name Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7Q6AEPower Alarm Q6 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
6Q5AE
Power Alarm Q5 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
5Q4AE
Power Alarm Q4 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
4Q3AE
Power Alarm Q3 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
3Q2AE
Power Alarm Q2 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
2Q1AE
Power Alarm Q1 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1LCIE
Loop Closure Transition Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0RTIE
Ring Trip Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Si3215
68 Rev. 0.92
Reset settings = 0000_0000
Register 23. Interrupt Enable 3
BitD7D6D5D4D3D2D1D0
Name INDE
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1INDE
Indirect Register Access Serviced Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0 Reserved Read returns zero.
Si3215
Rev. 0.92 69
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 28. Indirect Data Access—Low Byte
BitD7D6D5D4D3D2D1D0
Name IDA[7:0]
Type R/W
Bit Name Function
7:0 IDA[7:0] Indirect Data Access—Low Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 29. Indirect Data Access—High Byte
BitD7D6D5D4D3D2D1D0
Name IDA[15:8]
Type R/W
Bit Name Function
7:0 IDA[15:8] Indirect Data Access—High Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Si3215
70 Rev. 0.92
Reset settings = xxxx_xxxx
Reset settings = 0000_0000
Register 30. Indirect Address
BitD7D6D5D4D3D2D1D0
Name IAA[7:0]
Type R/W
Bit Name Function
7:0 IAA[7:0] Indirect Address Access.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 31. Indirect Address Status
BitD7D6D5D4D3D2D1D0
Name IAS
Type R
Bit Name Function
7:1 Reserved Read returns zero.
0IAS
Indirect Access Status.
0 = No indirect memory access pending.
1 = Indirect memory access pending.
Si3215
Rev. 0.92 71
Reset settings = 0000_0000
Register 32. Oscillator 1 Control
BitD7D6D5D4D3D2D1D0
Name OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0]
Type R R/W R/W R/W R/W R/W R/W
Bit Name Function
7 OSS1 Oscillator 1 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6REL
Oscillator 1 Automatic Register Reload.
This bit should be set for FSK signaling.
0 = Oscillator 1 will stop signaling after inactive timer expires.
1 = Oscillator 1 will continue to read register parameters and output signals.
5OZ1
Oscillator 1 Zero Cross Enable.
0 = Signal terminates after active timer expires.
1 = Signal terminates at zero crossing after active timer expires.
4O1TAE
Oscillator 1 Active Timer Enable.
0=Disable timer.
1 = Enable timer.
3O1TIE
Oscillator 1 Inactive Timer Enable.
0=Disable timer.
1 = Enable timer.
2O1E
Oscillator 1 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0 O1SO[1:0] Oscillator 1 Signal Output Routing.
00 = Unassigned path (output not connected).
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
Si3215
72 Rev. 0.92
Reset settings = 0000_0000
Register 33. Oscillator 2 Control
BitD7D6D5D4D3D2D1D0
Name OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0]
Type R R/W R/W R/W R/W R/W
Bit Name Function
7 OSS2 Oscillator 2 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6 Reserved Read returns zero.
5OZ2
Oscillator 2 Zero Cross Enable.
0 = Signal terminates after active timer expires.
1 = Signal terminates at zero crossing.
4O2TAE
Oscillator 2 Active Timer Enable.
0=Disable timer.
1 = Enable timer.
3O2TIE
Oscillator 2 Inactive Timer Enable.
0=Disable timer.
1 = Enable timer.
2O2E
Oscillator 2 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0 O2SO[1:0] Oscillator 2 Signal Output Routing.
00 = Unassigned path (output not connected)
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
Si3215
Rev. 0.92 73
Reset settings = 0000_0000
Register 34. Ringing Oscillator Control
BitD7D6D5D4D3D2D1D0
Name RSS RDAC RTAE RTIE ROE RVO TSWS
Type RRR/WR/WRR/WR/W
Bit Name Function
7RSSRinging Signal Status.
0 = Ringing oscillator output signal inactive.
1 = Ringing oscillator output signal active.
6 Reserved Read returns zero.
5 RDAC Ringing Signal DAC/Linefeed Cross Indicator.
For ringing signal start and stop, output to TIP and RING is suspended to ensure conti-
nuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at
TIP and RING.
0 = Ringing signal not present at TIP and RING.
1 = Ringing signal present at TIP and RING.
4RTAE
Ringing Active Timer Enable.
0=Disable timer.
1 = Enable timer.
3RTIE
Ringing Inactive Timer Enable.
0=Disable timer.
1 = Enable timer.
2ROE
Ringing Oscillator Enable.
0 = Ringing oscillator disabled.
1 = Ringing oscillator enabled.
1RVO
Ringing Voltage Offset.
0 = No dc offset added to ringing signal.
1 = DC offset added to ringing signal.
0 TSWS Trapezoid/Sinusoid Waveshape Select.
0 = Sinusoid
1 = Trapezoid
Si3215
74 Rev. 0.92
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 36. Oscillator 1 Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OAT1[7:0]
Type R/W
Bit Name Function
7:0 OAT1[7:0] Oscillator 1 Active Timer.
LSB = 125 µs
Register 37. Oscillator 1 Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OAT1[15:8]
Type R/W
Bit Name Function
7:0 OAT1[15:8] Oscillator 1 Active Timer.
Register 38. Oscillator 1 Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OIT1[7:0]
Type R/W
Bit Name Function
7:0 OIT1[7:0] Oscillator 1 Inactive Timer.
LSB = 125 µs
Si3215
Rev. 0.92 75
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 39. Oscillator 1 Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OIT1[15:8]
Type R/W
Bit Name Function
7:0 OIT1[15:8] Oscillator 1 Inactive Timer.
Register 40. Oscillator 2 Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OAT2[7:0]
Type R/W
Bit Name Function
7:0 OAT2[7:0] Oscillator 2 Active Timer.
LSB = 125 µs
Register 41. Oscillator 2 Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OAT2[15:8]
Type R/W
Bit Name Function
7:0 OAT2[15:8] Oscillator 2 Active Timer.
Si3215
76 Rev. 0.92
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 42. Oscillator 2 Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OIT2[7:0]
Type R/W
Bit Name Function
7:0 OIT2[7:0] Oscillator 2 Inactive Timer.
LSB = 125 µs
Register 43. Oscillator 2 Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OIT2[15:8]
Type R/W
Bit Name Function
7:0 OIT2[15:8] Oscillator 2 Inactive Timer.
Register 48. Ringing Oscillator Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name RAT[7:0]
Type R/W
Bit Name Function
7:0 RAT[7:0] Ringing Active Timer.
LSB = 125 µs
Si3215
Rev. 0.92 77
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 49. Ringing Oscillator Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name RAT[15:8]
Type R/W
Bit Name Function
7:0 RAT[15:8] Ringing Active Timer.
Register 50. Ringing Oscillator Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name RIT[7:0]
Type R/W
Bit Name Function
7:0 RIT[7:0] Ringing Inactive Timer.
LSB = 125 µs
Register 51. Ringing Oscillator Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name RIT[15:8]
Type R/W
Bit Name Function
7:0 RIT[15:8] Ringing Inactive Timer.
Si3215
78 Rev. 0.92
Reset settings = 0000_0000
Reset settings = 0101_0100
Register 52. FSK Data
BitD7D6D5D4D3D2D1D0
Name FSKDAT
Type R/W
Bit Name Function
7:1 Reserved Read returns zero.
0 FSKDAT FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream data.
Register 63. Loop Closure Debounce Interval
BitD7D6D5D4D3D2D1D0
Name LCD[7:0]
Type
Bit Name Function
7:0 LCD[7:0] Loop Closure Debounce Interval for Automatic Ringing.
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
Si3215
Rev. 0.92 79
Reset settings = 0000_0000
Register 64. Linefeed Control
BitD7D6D5D4D3D2D1D0
Name LFS[2:0] LF[2:0]
Type RR/W
Bit Name Function
7 Reserved Read returns zero.
6:4 LFS[2:0] Linefeed Shadow.
This register reflects the actual real time linefeed state. Automatic operations may cause
actual linefeed state to deviate from the state defined by linefeed register (e.g., when
linefeed equals ringing state, LFS will equal on-hook transmission state during ringing
silent period and ringing state during ring burst).
000 = Open
001 = Forward active
010 = Forward on-hook transmission
011 = TIP open
100 = Ringing
101 = Reverse active
110 = Reverse on-hook transmission
111 = RING open
3 Reserved Read returns zero.
2:0 LF[2:0] Linefeed.
Writing to this register sets the linefeed state.
000 = Open
001 = Forward active
010 = Forward on-hook transmission
011 = TIP open
100 = Ringing
101 = Reverse active
110 = Reverse on-hook transmission
111 = RING open
Si3215
80 Rev. 0.92
Reset settings = 0110_0001
Register 65. External Bipolar Transistor Control
BitD7D6D5D4D3D2D1D0
Name SQH CBY ETBE ETBO[1:0] ETBA[1:0]
Type R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6SQH
Audio Squelch.
0 = No squelch.
1 = STIPAC and SRINGAC pins squelched.
5CBY
Capacitor Bypass.
0 = Capacitors CP (C1) and CM (C2) in circuit.
1 = Capacitors CP (C1) and CM (C2) bypassed.
4ETBE
External Transistor Bias Enable.
0 = Bias disabled.
1 = Bias enabled.
3:2 ETBO[1:0] External Transistor Bias Levels—On-Hook Transmission State.
DC bias current which flows through external BJTs in the on-hook transmission state.
Increasing this value increases the compliance of the ac longitudinal balance circuit.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
1:0 ETBA[1:0] External Transistor Bias Levels—Active Off-Hook State.
DC bias current which flows through external BJTs in the active off-hook state. Increasing
this value increases the compliance of the ac longitudinal balance circuit.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
Si3215
Rev. 0.92 81
Reset settings = 0000_0011
Register 66. Battery Feed Control
BitD7D6D5D4D3D2D1D0
Name VOV FVBAT TRACK
Type R/W R/W R/W
Bit Name Function
7:5 Reserved Read returns zero.
4VOV
Overhead Voltage Range Increase.
This bit selects the programmable range for VOV
, which is defined in indirect Register 64.
0=V
OV = 0 V to 9 V
1=V
OV = 0 V to 13.5 V
3FVBAT
VBAT Manual Setting.
0 = Normal operation
1=V
BAT tracks VBATH register.
2:1 Reserved Read returns zero.
0TRACK
DC-DC Converter Tracking Mode.
0=|V
BAT| will not decrease below VBATL.
1=V
BAT tracks VRING
.
Si3215
82 Rev. 0.92
Reset settings = 0001_1111
Register 67. Automatic/Manual Control
BitD7D6D5D4D3D2D1D0
Name MNCM MNDIF SPDS AORD AOLD AOPN
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 MNCM Common Mode Manual/Automatic Select.
0=Automatic control.
1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow
VCM value.
5 MNDIF Differential Mode Manual/Automatic Select.
0=Automatic control.
1 = Manual control (forces differential voltage to follow VOC value).
4 SPDS Speed-Up Mode Enable.
0 = Speed-up disabled.
1 = Automatic speed-up.
3 Reserved Read returns zero.
2AORD
Automatic/Manual Ring Trip Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon ring trip detect.
1AOLD
Automatic/Manual Loop Closure Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon loop closure detect.
0AOPN
Power Alarm Automatic/Manual Detect.
0 = Manual mode.
1 = Enter open state automatically upon power alarm.
Si3215
Rev. 0.92 83
Reset settings = 0000_0000
Reset settings = 0000_1010
Register 68. Loop Closure/Ring Trip Detect Status
BitD7D6D5D4D3D2D1D0
Name DBIRAW RTP LCR
Type RRR
Bit Name Function
7:3 Reserved Read returns zero.
2DBIRAW
Ring Trip/Loop Closure Unfiltered Output.
State of this bit reflects the real time output of ring trip and loop closure detect circuits
before debouncing.
0 = Ring trip/loop closure threshold exceeded.
1 = Ring trip/loop closure threshold not exceeded.
1RTP
Ring Trip Detect Indicator (Filtered Output).
0 = Ring trip detect has not occurred.
1 = Ring trip detect occurred.
0LCR
Loop Closure Detect Indicator (Filtered Output).
0 = Loop closure detect has not occurred.
1 = Loop closure detect has occurred.
Register 69. Loop Closure Debounce Interval
BitD7D6D5D4D3D2D1D0
Name LCDI[6:0]
Type R/W
Bit Name Function
7 Reserved Read returns zero.
6:0 LCDI[6:0] Loop Closure Debounce Interval.
The value written to this register defines the minimum steady state debounce time. Value
may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Si3215
84 Rev. 0.92
Reset settings = 0000_1010
Reset settings = 0000_0000
Register 70. Ring Trip Detect Debounce Interval
BitD7D6D5D4D3D2D1D0
Name RTDI[6:0]
Type R/W
Bit Name Function
7 Reserved Read returns zero.
6:0 RTDI[6:0] Ring Trip Detect Debounce Interval.
The value written to this register defines the minimum steady state debounce time. The
value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Register 71. Loop Current Limit
BitD7D6D5D4D3D2D1D0
Name ILIM[2:0]
Type R/W
Bit Name Function
7:3 Reserved Read returns zero.
2:0 ILIM[2:0] Loop Current Limit.
The value written to this register sets the constant loop current. The value may be set
between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps.
Si3215
Rev. 0.92 85
Reset settings = 0010_0000
Reset settings = 0000_0010
Register 72. On-Hook Line Voltage
BitD7D6D5D4D3D2D1D0
Name VSGN VOC[5:0]
Type R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 VSGN On-Hook Line Voltage.
The value written to this bit sets the on-hook line voltage polarity (VTIP–VRING).
0=V
TIP–VRINGis positive
1=V
TIP–VRING is negative
5:0 VOC[5:0] On-Hook Line Voltage.
The value written to this register sets the on-hook line voltage (VTIP–VRING). Value may
be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V.
Register 73. Common Mode Voltage
BitD7D6D5D4D3D2D1D0
Name VCM[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VCM[5:0] Common Mode Voltage.
The value written to this register sets VTIP for forward active and forward on-hook trans-
mission states and VRING for reverse active and reverse on-hook transmission states.
The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default
value = –3 V.
Si3215
86 Rev. 0.92
Reset settings = 0011_0010
Reset settings = 0001_0000
Register 74. High Battery Voltage
BitD7D6D5D4D3D2D1D0
Name VBATH[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VBATH[5:0] High Battery Voltage.
The value written to this register sets high battery voltage. VBATH must be greater than
or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in
1.5 V steps. Default value = –75 V. For Si3211, VBATH must be set equal to externally
supplied VBATH input voltage.
Register 75. Low Battery Voltage
BitD7D6D5D4D3D2D1D0
Name VBATL[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VBATL[5:0] Low Battery Voltage.
The value written to this register sets low battery voltage. VBATH must be greater than or
equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V
steps. Default value = –24 V. For Si3211, VBATL must be set equal to externally supplied
VBATL input voltage.
Si3215
Rev. 0.92 87
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 76. Power Monitor Pointer
BitD7D6D5D4D3D2D1D0
Name PWRMP[2:0]
Type R/W
Bit Name Function
7:3 Reserved Read returns zero.
2:0 PWRMP[2:0] Power Monitor Pointer.
Selects the external transistor from which to read power output. The power of the
selected transistor is read in the PWROM register.
000 = Q1
001 = Q2
010 = Q3
011 = Q4
100 = Q5
101 = Q6
110 = Undefined
111 = Undefined
Register 77. Line Power Output Monitor
BitD7D6D5D4D3D2D1D0
Name PWROM[7:0]
Type R
Bit Name Function
7:0 PWROM[7:0] Line Power Output Monitor.
This register reports the real time power output of the transistor selected using PWRMP.
The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6.
The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4.
Si3215
88 Rev. 0.92
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 78. Loop Voltage Sense
BitD7D6D5D4D3D2D1D0
Name LVSP LVS[5:0]
Type RR
Bit Name Function
7 Reserved Read returns zero.
6LVSP
Loop Voltage Sense Polarity.
This register reports the polarity of the differential loop voltage (VTIP – VRING).
0 = Positive loop voltage (VTIP > VRING).
1 = Negative loop voltage (VTIP < VRING).
5:0 LVS[5:0] Loop Voltage Sense Magnitude.
This register reports the magnitude of the differential loop voltage (VTIP–VRING). The
range is 0 V to 94.5 V in 1.5 V steps.
Register 79. Loop Current Sense
BitD7D6D5D4D3D2D1D0
Name LCSP LCS[5:0]
Type RR
Bit Name Function
7 Reserved Read returns zero.
6LCSP
Loop Current Sense Polarity.
This register reports the polarity of the loop current.
0 = Positive loop current (forward direction).
1 = Negative loop current (reverse direction).
5:0 LCS[5:0] Loop Current Sense Magnitude.
This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in
1.25 mA steps.
Si3215
Rev. 0.92 89
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 80. TIP Voltage Sense
BitD7D6D5D4D3D2D1D0
Name VTIP[7:0]
Type R
Bit Name Function
7:0 VTIP[7:0] TIP Voltage Sense.
This register reports the real time voltage at TIP with respect to ground. The range is 0 V
(0x00) to –95.88 V (0xFF) in .376 V steps.
Register 81. RING Voltage Sense
BitD7D6D5D4D3D2D1D0
Name VRING[7:0]
Type R
Bit Name Function
7:0 VRING[7:0] RING Voltage Sense.
This register reports the real time voltage at RING with respect to ground. The range is
0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Register 82. Battery Voltage Sense 1
BitD7D6D5D4D3D2D1D0
Name VBATS1[7:0]
Type R
Bit Name Function
7:0 VBATS1[7:0] Battery Voltage Sense 1.
This register is one of two registers that reports the real time voltage at VBAT with respect
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Si3215
90 Rev. 0.92
Reset settings = 0000_0000
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Register 83. Battery Voltage Sense 2
BitD7D6D5D4D3D2D1D0
Name VBATS2[7:0]
Type R
Bit Name Function
7:0 VBATS2[7:0] Battery Voltage Sense 2.
This register is one of two registers that reports the real time voltage at VBAT with respect
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Register 84. Transistor 1 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ1[7:0]
Type R
Bit Name Function
7:0 IQ1[7:0] Transistor 1 Current Sense.
This register reports the real time current through Q1. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
Register 85. Transistor 2 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ2[7:0]
Type R
Bit Name Function
7:0 IQ2[7:0] Transistor 2 Current Sense.
This register reports the real time current through Q2. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
Si3215
Rev. 0.92 91
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Register 86. Transistor 3 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ3[7:0]
Type R
Bit Name Function
7:0 IQ3[7:0] Transistor 3 Current Sense.
This register reports the real time current through Q3. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 87. Transistor 4 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ4[7:0]
Type R
Bit Name Function
7:0 IQ4[7:0] Transistor 4 Current Sense.
This register reports the real time current through Q4. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 88. Transistor 5 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ5[7:0]
Type R
Bit Name Function
7:0 IQ5[7:0] Transistor 5 Current Sense.
This register reports the real time current through Q5. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Si3215
92 Rev. 0.92
Reset settings = xxxx_xxxx
Reset settings = 1111_1111
Register 89. Transistor 6 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ6[7:0]
Type R
Bit Name Function
7:0 IQ6[7:0] Transistor 6 Current Sense.
This register reports the real time current through Q6. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Register 92. DC-DC Converter PWM Period
BitD7D6D5D4D3D2D1D0
Name DCN[7] 1 DCN[5:0]
Type R/W R R/W
Bit Name Function
7:0 DCN[7:0] DC-DC Converter Period.
This register sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40)
to 15.564 µs (0xFF) in 61.035 ns steps.
Bit 6 is fixed to one and read-only, so there are two ranges of operation:
3.906–7.751 µs, used for MOSFET transistor switching.
11.719–15.564 µs, used for BJT transistor switching.
Si3215
Rev. 0.92 93
Reset settings = 0001_0100 (Si3215)
Reset settings = 0011_0100 (Si3215M)
Register 93. DC-DC Converter Switching Delay
Si3215
BitD7D6D5D4D3D2D1D0
Name DCCAL DCPOL DCTOF[4:0]
Type R/W R R/W
Bit Name Function
7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status.
Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine.
0 = Normal operation.
1 = Calibration being performed.
6 Reserved Read returns zero.
5 DCPOL DC-DC Converter Feed Forward Pin (DCFF) Polarity.
This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV
pin. Two versions of the Si3215 are offered to support the two relationships.
0 = DCFF pin polarity is opposite of DCDRV pin (Si3215).
1 = DCFF pin polarity is same as DCDRV pin (Si3215M).
4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time.
This register sets the minimum off time for the pulse width modulated dc-dc
converter control. TOFF =(DCTOF + 4)
61.035 ns.
Si3215
94 Rev. 0.92
Reset settings = 0000_0000
Register 94. DC-DC Converter PWM Pulse Width
BitD7D6D5D4D3D2D1D0
Name DCPW[7:0]
Type R
Bit Name Function
7:0 DCPW[7:0] DC-DC Converter Pulse Width.
Pulse width of DCDRV is given by PW = (DCPW – DCTOF – 4) x 61.035 ns.
Si3215
Rev. 0.92 95
Reset settings = 0001_1111
Register 96. Calibration Control/Status Register 1
BitD7D6D5D4D3D2D1D0
Name CAL CALSP CALR CALT CALD CALC CALIL
Type R/WR/WR/WR/WR/WR/WR/W
Bit Name Function
7 Reserved Read returns zero.
6CAL
Calibration Control/Status Bit.
Setting this bit begins calibration of the entire system.
0 = Normal operation or calibration complete.
1 = Calibration in progress.
5 CALSP Calibration Speedup.
Setting this bit shortens the time allotted for VBAT settling at the beginning of the
calibration cycle.
0 = 300 ms
1=30ms
4CALR
RING Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Reference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
3CALT
TIP Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Reference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
2CALD
Differential DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
1CALC
Common Mode DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
0CALIL
ILIM Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Si3215
96 Rev. 0.92
Reset settings = 0001_1111
Register 97. Calibration Control/Status Register 2
BitD7D6D5D4D3D2D1D0
Name CALM1 CALM2 CALDAC CALADC CALCM
Type R/WR/WR/WR/WR/W
Bit Name Function
7:5 Reserved Read returns zero.
4CALM1
Monitor ADC Calibration 1.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
3CALM2
Monitor ADC Calibration 2.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
2CALDAC
DAC Calibration.
Setting this bit begins calibration of the audio DAC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
1 CALADC ADC Calibration.
Setting this bit begins calibration of the audio ADC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
0CALCM
Common Mode Balance Calibration.
Setting this bit begins calibration of the ac longitudinal balance.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Si3215
Rev. 0.92 97
Reset settings = 0001_0000
Reset settings = 0001_0000
Reset settings = 0001_0001
Register 98. RING Gain Mismatch Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGMR[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current.
Register 99. TIP Gain Mismatch Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGMT[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current.
Register 100. Differential Loop Current Gain Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGD[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
4:0 CALGD[4:0] Differential DAC Gain Calibration Result.
Si3215
98 Rev. 0.92
Reset settings = 0001_0001
Reset settings = 0000_1000
Reset settings = 1000_1000
Register 101. Common Mode Loop Current Gain Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGC[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result.
Register 102. Current Limit Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGIL[3:0]
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
3:0 CALGIL[3:0] Current Limit Calibration Result.
Register 103. Monitor ADC Offset Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALMG1[3:0] CALMG2[3:0]
Type R/W R/W
Bit Name Function
7:4 CALMG1[3:0] Monitor ADC Offset Calibration Result 1.
3:0 CALMG2[3:0] Monitor ADC Offset Calibration Result 2.
Si3215
Rev. 0.92 99
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_1000
Register 104. Analog DAC/ADC Offset
BitD7D6D5D4D3D2D1D0
Name DACP DACN ADCP ADCN
Type R/W R/W R/W R/W
Bit Name Function
7:4 Reserved Read returns zero.
3DACP
Positive Analog DAC Offset.
2DACNNegative Analog DAC Offset.
1 ADCP Positive Analog ADC Offset.
0ADCNNegative Analog ADC Offset.
Register 105. DAC Offset Calibration Result
BitD7D6D5D4D3D2D1D0
Name DACOF[7:0]
Type R/W
Bit Name Function
7:0 DACOF[7:0] DAC Offset Calibration Result.
Register 107. DC Peak Current Monitor Calibration Result
BitD7D6D5D4D3D2D1D0
Name CMDCPK[3:0]
Type R/W
Bit Name Function
7:4 Reserved Read returns zero.
3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result.
Si3215
100 Rev. 0.92
Reset settings = 0000_0000
Register 108. Enhancement Enable
BitD7D6D5D4D3D2D1D0
Name ILIMEN FSKEN DCSU LCVE DCFIL HYSTEN
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7ILIMENCurrent Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
6 FSKEN FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 69–74). Audio tones are generated using this
new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolu-
tion of 41.67 µs. This provides greater resolution during FSK caller ID signal generation.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
5 DCSU DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
4:3 Reserved Read returns zero.
2LCVE
Voltage-Based Loop Closure.
Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur-
rent.
0 = Loop closure determined by loop current.
1 = Loop closure determined by TIP-to-RING voltage.
1DCFIL
DC-DC Converter Squelch.
When enabled, this bit squelches noise in the audio band from the dc-dc converter con-
trol loop.
0 = Voice band squelch disabled.
1 = Voice band squelch enabled.
0 HYSTEN Loop Closure Hysteresis Enable.
When enabled, this bit allows hysteresis to the loop closure calculation. The upper and
lower hysteresis thresholds are defined by indirect registers 15 and 66, respectively.
0 = Loop closure hysteresis disabled.
1 = Loop closure hysteresis enabled.
Si3215
Rev. 0.92 101
4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A
write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the
contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.
A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the
value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of
16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an
interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
Table 34. Si3210 to Si3215 Indirect Register Cross Reference
Si3210
Indirect
Register
Si3215
Indirect
Register
Indirect
Register
Name
Si3210
Indirect
Register
Si3215
Indirect
Register
Indirect
Register
Name
Si3210
Indirect
Register
Si3215
Indirect
Register
Indirect
Register
Name
13 0 OSC1 27 14 ADCG 38 25 NQ34
14 1 OSC1X 28 15 LCRT 39 26 NQ56
15 2 OSC1Y 29 16 RPTP 40 27 VCMR
16 3 OSC2 30 17 CML 41 64 VMIND
17 4 OSC2X 31 18 CMH 43 66 LCRTL
18 5 OSC2Y 32 19 PPT12 99 69 FSK0X
19 6 ROFF 33 20 PPT34 100 70 FSK0
20 7 RCO 34 21 PPT56 101 71 FSK1X
21 8 RNGX 35 22 NCLR 102 72 FSK1
22 9 RNGY 36 23 NRTP 103 73 FSK01
26 13 DACG 37 24 NQ12 104 74 FSK10
Si3215
102 Rev. 0.92
4.1. Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing
register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but should be written to zeroes.
Table 35. Oscillator Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
0 OSC1[15:0]
1 OSC1X[15:0]
2 OSC1Y[15:0]
3 OSC2[15:0]
4 OSC2X[15:0]
5 OSC2Y[15:0]
6ROFF[5:0]
7 RCO[15:0]
8 RNGX[15:0]
9 RNGY[15:0]
Table 36. Oscillator Indirect Registers Description
Address Description Reference Page
0Oscillator 1 Frequency Coefficient.
Sets tone generator 1 frequency.
33
1Oscillator 1 Amplitude Register.
Sets tone generator 1 signal amplitude.
33
2Oscillator 1 Initial Phase Register.
Sets initial phase of tone generator 1 signal.
33
3Oscillator 2 Frequency Coefficient.
Sets tone generator 2 frequency.
33
4Oscillator 2 Amplitude Register.
Sets tone generator 2 signal amplitude.
33
5Oscillator 2 Initial Phase Register.
Sets initial phase of tone generator 2 signal.
33
6Ringing Oscillator DC Offset.
Sets dc offset component (VTIP–VRING) to ringing waveform.
The range is 0 to 94.5 V in 1.5 V increments.
35
Si3215
Rev. 0.92 103
4.2. Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register
values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but should be written to zeroes.
7Ringing Oscillator Frequency Coefficient.
Sets ringing generator frequency.
35
8Ringing Oscillator Amplitude Register.
Sets ringing generator signal amplitude.
35
9Ringing Oscillator Initial Phase Register.
Sets initial phase of ringing generator signal.
35
Table 37. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
13 DACG[11:0]
14 ADCG[11:0]
Table 38. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr. Description Reference
Page
13 Receive Path Digital to Analog Converter Gain/Attenuation.
This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-
tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to –∞dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
39
14 Transmit Path Analog to Digital Converter Gain/Attenuation.
This register sets gain/attenuation for the transmit path. The digitized signal is effectively
multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –∞dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
39
Table 36. Oscillator Indirect Registers Description (Continued)
Address Description Reference Page
Si3215
104 Rev. 0.92
4.3. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but should be written to zeroes.
Table 39. SLIC Control Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
15 LCRT[5:0]
16 RPTP[5:0]
17 CML[5:0]
18 CMH[5:0]
19 PPT12[7:0]
20 PPT34[7:0]
21 PPT56[7:0]
22 NCLR[12:0]
23 NRTP[12:0]
24 NQ12[12:0]
25 NQ34[12:0]
26 NQ56[12:0]
27 VCMR[3:0]
64 VMIND[3:0]
66 LCRTL[5:0]
Table 40. SLIC Control Indirect Registers Description
Addr. Description Reference Page
15 Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
28
16 Ring Trip Threshold.
Ring trip detection threshold during ringing.
38
17 Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
18 Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
19 Power Alarm Threshold for Transistors Q1 and Q2. 27
Si3215
Rev. 0.92 105
4.4. FSK Control
For detailed instructions on FSK signal generation, refer to “AN32: FSK Generation”. These registers support
enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1
(direct Register 32, bit 6).
20 Power Alarm Threshold for Transistors Q3 and Q4. 27
21 Power Alarm Threshold for Transistors Q5 and Q6. 27
22 Loop Closure Filter Coefficient. 28
23 Ring Trip Filter Coefficient. 38
24 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. 27
25 Thermal Low Pass Filter Pole for Transistors Q3 and Q4. 27
26 Thermal Low Pass Filter Pole for Transistors Q5 and Q6. 27
27 Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal.
35
64 DC-DC Converter VOV Voltage.
This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter.
When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V
(VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V
(VMIND = 0 to 9h).
29
66 Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
28
Table 41. FSK Control Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
69 FSK0X[15:0]
70 FSK0[15:0]
71 FSK1X[15:0]
72 FSK1[15:0]
73 FSK01[15:0]
74 FSK10[15:0]
Table 40. SLIC Control Indirect Registers Description (Continued)
Addr. Description Reference Page
Si3215
106 Rev. 0.92
Table 42. FSK Control Indirect Registers Description
Addr Description Reference Page
69 FSK Amplitude Coefficient for Space.
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a space or “0”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1X.
35 and AN32
70 FSK Frequency Coefficient for Space.
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a space or “0”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1.
35 and AN32
71 FSK Amplitude Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1X.
35 and AN32
72 FSK Frequency Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1.
35 and AN32
73 FSK Transition Parameter from 0 to 1.
When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is
applied to signal amplitude when transitioning from a space (0) to a mark (1).
35 and AN32
74 FSK Transition Parameter from 1 to 0.
When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is
applied to signal amplitude when transitioning from a mark (1) to a space (0).
35 and AN32
Si3215
Rev. 0.92 107
5. Pin Descriptions: Si3215
Pin #
QFN
Pin #
TSSOP Name Description
35 1 CS Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance.
When active, the serial port is operational.
36 2 INT Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
37 3 PCLK PCM Bus Clock.
Clock input for PCM bus timing.
38 4 DRX Receive PCM Data.
Input data from PCM bus.
15DTX
Transmit PCM Data.
Output data to PCM bus.
2 6 FSYNC Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse for-
mat.
3 7 RESET Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
4 8 SDCH DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
TSSOP
27
28
29
30
31
34
33
32
CS
INT
PCLK
DTX
FSYNC
RESET
SDCH
SCLK
SDI
SDITHRU
SDO
DCFF
DCDRV
GNDD
TEST
DRX
1
2
3
4
5
6
7
8
9
10
11
12
13 26
25
14
SDCL
VDDA1
IREF
CAPP
ITIPN
VDDD
VDDA2
ITIPP
35
36
37
38
QGND
CAPM
IRINGP
IRINGN
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
IGMP
GNDA
IGMN
SRINGAC
STIPAC
15
16
17
18
19
24
23
22
21
20
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35363738
15 16 17 18 19
24
23
22
21
20
QFN
DTX
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST
DCFF
DCDRV
SDITHRU
SDO
SDI
SCLK
CS
INT
PCLK
DRX
Si3215
108 Rev. 0.92
5 9 SDCL DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
610V
DDA1 Analog Supply Voltage.
Analog power supply for internal analog circuitry.
711IREF
Current Reference.
Connects to an external resistor used to provide a high accuracy reference current.
8 12 CAPP SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
913QGND
Component Reference Ground.
10 14 CAPM SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
11 15 STIPDC TIP Sense.
Analog current input used to sense voltage on the TIP lead.
12 16 SRINGDC RING Sense.
Analog current input used to sense voltage on the RING lead.
13 17 STIPE TIP Emitter Sense.
Analog current input used to sense voltage on the Q6 emitter lead.
14 18 SVBAT VBAT Sense.
Analog current input used to sense voltage on dc-dc converter output voltage lead.
15 19 SRINGE RING Emitter Sense.
Analog current input used to sense voltage on the Q5 emitter lead.
16 20 STIPAC TIP Transmit Input.
Analog ac input used to detect voltage on the TIP lead.
17 21 SRINGAC RING Transmit Input.
Analog ac input used to detect voltage on the RING lead.
18 22 IGMN Transconductance Amplifier External Resistor.
Negative connection for transconductance gain setting resistor.
19 23 GNDA Analog Ground.
Ground connection for internal analog circuitry.
20 24 IGMP Transconductance Amplifier External Resistor.
Positive connection for transconductance gain setting resistor.
21 25 IRINGN Negative Ring Current Control.
Analog current output driving Q3.
22 26 IRINGP Positive Ring Current Control.
Analog current output driving Q2.
23 27 VDDA2 Analog Supply Voltage.
Analog power supply for internal analog circuitry.
Pin #
QFN
Pin #
TSSOP Name Description
Si3215
Rev. 0.92 109
24 28 ITIPP Positive TIP Current Control.
Analog current output driving Q1.
25 29 ITIPN Negative TIP Current Control.
Analog current output driving Q4.
26 30 VDDD Digital Supply Voltage.
Digital power supply for internal digital circuitry.
27 31 GNDD Digital Ground.
Ground connection for internal digital circuitry.
28 32 TEST Test.
Enables test modes for Silicon Labs internal testing. This pin should always be tied
to ground for normal operation.
29 33 DCFF DC Feed-Forward/High Current General Purpose Output.
Feed-forward drive of external bipolar transistors to improve dc-dc converter
efficiency.
30 34 DCDRV DC Drive/Battery Switch.
DC-DC converter control signal output which drives external bipolar transistor.
31 35 SDITHRU SDI Passthrough.
Cascaded SDI output signal for daisy-chain mode.
32 36 SDO Serial Port Data Out.
Serial port control data output.
33 37 SDI Serial Port Data In.
Serial port control data input.
34 38 SCLK Serial Port Bit Clock Input.
Serial port clock input. Controls the serial data on SDO and latches the data on SDI.
Pin #
QFN
Pin #
TSSOP Name Description
Si3215
110 Rev. 0.92
6. Pin Descriptions: Si3201
Pin # Name Input/
Output
Description
1 TIP I/O TIP Output—Connect to the TIP lead of the subscriber loop.
2, 6, 9, 12 NC — No Internal Connection—Do not connect to any electrical signal.
3 RING I/O RING Output—Connect to the RING lead of the subscriber loop.
4VBAT—
Operating Battery Voltage—Connect to the battery supply.
5VBATH—
High Battery Voltage—This pin is internally connected to VBAT.
7GND—
Ground—Connect to a low impedance ground plane.
8VDD—
Supply Voltage—Main power supply for all internal circuitry. Connect to a
3.3 V or 5 V supply. Decouple locally with a 0.1 µF/6 V capacitor.
10 SRINGE O RING Emitter Sense Output—Connect to the SRINGE pin of the Si321x
pin.
11 STIPE O TIP Emitter Sense Output—Connect to the STIPE pin of the Si321x pin.
13 IRINGN I Negative RING Current Control—Connect to the IRINGN lead of the
Si321x.
14 IRINGP I Positive RING Current Drive—Connect to the IRINGP lead of the Si321x.
15 ITIPN I Negative TIP Current Control—Connect to the ITIPN lead of the Si321x.
16 ITIPP I Positive TIP Current Control—Connect to the ITIPP lead of the Si321x.
Bottom-Side
Exposed Pad
—Exposed Thermal Pad—Connect to the bulk ground plane.
116
215
314
413
512
611
710
89
ITIPP
IRINGP
IRINGN
NC
STIPE
SRINGE
NC
ITIPN
TIP
NC
RING
VBATH
GND
NC
VDD
VBAT
Si3215
Rev. 0.92 111
7. Ordering Guide
Device Description DCFF Pin Package Lead-Free and
RoHS-Compliant
Temp Range
Si3215-X-FM ProSLIC DCDRV QFN-38 Yes 0 to 70 °C
Si3215-X-GM ProSLIC DCDRV QFN-38 Yes –40 to 85 °C
Si3215M-X-FM ProSLIC DCDRV QFN-38 Yes 0 to 70 °C
Si3215M-X-GM ProSLIC DCDRV QFN-38 Yes –40 to 85 °C
Si3215-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 °C
Si3215-GT ProSLIC DCDRV TSSOP-38 Yes –40 to 85 °C
Si3215M-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 °C
Si3215M-GT ProSLIC DCDRV TSSOP-38 Yes –40 to 85 °C
Si3215-KT ProSLIC DCDRV TSSOP-38 No 0 to 70 °C
Si3215-BT ProSLIC DCDRV TSSOP-38 No –40 to 85 °C
Si3215M-KT ProSLIC DCDRV TSSOP-38 No 0 to 70 °C
Si3215M-BT ProSLIC DCDRV TSSOP-38 No –40 to 85 °C
Si3201-FS Line Interface N/A SOIC-16 Yes 0 to 70 °C
Si3201-GS Line Interface N/A SOIC-16 Yes –40 to 85 °C
Si3201-KS Line Interface N/A SOIC-16 No 0 to 70 °C
Si3201-BS Line Interface N/A SOIC-16 No –40 to 85 °C
Notes:
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
Si3215
112 Rev. 0.92
Table 43. Evaluation Kit Ordering Guide
Item Supported
ProSLIC
Description Linefeed
Interface
Si3215PPQX-EVB Si3215-QFN Evaluation Board, Daughter Card Discrete
Si3215PPQ1-EVB Si3215-QFN Evaluation Board, Daughter Card Si3201
Si3215DCQX-EVB Si3215-QFN Daughter Card Only Discrete
Si3215DCQ1-EVB Si3215-QFN Daughter Card Only Si3201
Si3215MPPQX-EVB Si3215M-QFN Evaluation Board, Daughter Card Discrete
Si3215MPPQ1-EVB Si3215M-QFN Evaluation Board, Daughter Card Si3201
Si3215MDCQX-EVB Si3215M-QFN Daughter Card Only Discrete
Si3215MDCQ1-EVB Si3215M-QFN Daughter Card Only Si3201
Si3215
Rev. 0.92 113
8. Package Outline: 38-Pin QFN
Figure 31 illustrates the package details for the Si321x. Table 44 lists the values for the dimensions shown in the
illustration.
Figure 31. 38-Pin Quad Flat No-Lead Package (QFN)
Table 44. Package Diagram Dimensions1,2,3
Symbol
Millimeters
Min Nom Max
A 0.75 0.85 0.95
A1 0.00 0.01 0.05
b 0.18 0.23 0.30
D5.00 BSC.
D2 3.10 3.20 3.30
e0.50 BSC.
E7.00 BSC.
E2 5.10 5.20 5.30
L 0.35 0.45 0.55
L1 0.03 0.05 0.08
aaa — — 0.10
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. Recommended card reflow profile is per the JEDEC/IPC
J-STD-020C specification for Small Body Components.
Bottom Side
Exposed Pad
3.2 x 5.2 mm
Si3215
114 Rev. 0.92
9. Package Outline: 38-Pin TSSOP
Figure 32 illustrates the package details for the Si321x. Table 45 lists the values for the dimensions shown in the
illustration.
Figure 32. 38-Pin Thin Shrink Small Outline Package (TSSOP)
Table 45. Package Diagram Dimensions
Symbol
Millimeters
Min Nom Max
A— —1.20
A1 0.05 — 0.15
b 0.17 — 0.27
c 0.09 — 0.20
D9.609.70
9.80
e 0.50 BSC
E 6.40 BSC
E1 4.30 4.40 4.50
L 0.450.600.75
θ0° — 8°
aaa 0.10
bbb 0.08
ccc 0.05
ddd 0.20
E1 E
e
D
L
θ
C
A
A1
b
E/2
bbb C B A
M
2x
ddd C B A
Accc
38x
aaa C
Seating Plane
C
Approximate device weight is 115.7 mg
2x
B
Si3215
Rev. 0.92 115
10. Package Outline: 16-Pin ESOIC
Figure 33 illustrates the package details for the Si3201. Table 46 lists the values for the dimensions shown in the
illustration.
Figure 33. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 46. Package Diagram Dimensions
Symbol
Millimeters
Min Max
A1.351.75
A1 0 0.15
B.33.51
C.19.25
D 9.80 10.00
E3.804.00
e 1.27 BSC
H5.806.20
h.25.50
L .40 1.27
γ—0.10
θ0º 8º
E H
A1
B
C
h
L
θ
eSee Detail F
Detail F
A
16 9
8
1
D
Seating Plane γ
Bottom Side
Exposed Pad
2.3 x 3.6 mm
Weight: Approximate device weight is 0.15 grams.
–C–
–A–
–B–
.25 M C A M B S
.25 M B M
x45°
Si3215
116 Rev. 0.92
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.91
Separated the Si3216/15 document into two data
sheets.
Added QFN package graphic to cover page.
Corrected EVB ordering part numbers.
Revision 0.91 to Revision 0.92
Figure 12, “Si3215/Si3215M Typical Application
Circuit Using Discrete Components,” on page 20.
Added optional components to application schematic to
improve idle channel noise.
"Register 10. Two-Wire Impedance Synthesis
Control" on page 59.
Corrected description for China impedance from
“(200 Ω + 600 Ω || 100 nF)” to “200 Ω + (680 Ω ||
100 nF)”.
"7. Ordering Guide" on page 111.
Updated to include product revision designator
Table 43, “Evaluation Kit Ordering Guide,” on
page 112.
Updated to include “M” version of device.
Table 15, “Si3215/Si3215M External Component
Values—Discrete Solution,” on page 20.
Added TO-92 transistor suppliers to BOM.
Table 46, “Package Diagram Dimensions,” on
page 115
Changed A1 max from 0.10 to 0.15.
Rev. C Si3215 Silicon:
Register 14, “Powerdown Control 1,” on page 61.
Changed Bit 3 from “Monitor ADC Power-Off Control” to
“PLL Free-Run Control”.
Si3215
Rev. 0.92 117
NOTES:
Si3215
118 Rev. 0.92
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: ProSLICinfo@silabs.com
Internet: www.silabs.com
Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
