| FAIRCHILD ree SEMICONDUCTOR MM74HC161 MM74HC163 September 1983 Revised February 1999 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear General Description The MM74HC161 and MM74HC163 synchronous presetta- ble counters utilize advanced silicon-gate CMOS technol- ogy and internal look-ahead carry logic for use in high speed counting applications. They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL. The HC161 and the HC163 are 4 bit binary counters. All flip-flops are clocked simultaneously on the LOW-to-HIGH transition (positive edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Pre- setting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held LOW counting is disabled and the data on the A, B, , and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken HIGH before the positive edge of CLOCK the count operation will be unaffected. All of these counters may be cleared by utilizing the CLEAR input. The clear function on the MM74HC163 counter is synchronous to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held LOW. The MM74HC161 counter is cleared asynchronously. When the CLEAR is taken LOW the counter is cleared immediately regardless of the CLOCK. Two active HIGH enable inputs (ENP and ENT) and a RIP- PLE CARRY (RC) output are provided to enable easy cas- cading of counters. Both ENABLE inputs must be HIGH to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the HIGH level portion of the Qa output. The RC output is fed to successive cascaded stages to facilitate easy imple- mentation of N-bit counters. All inputs are protected from damage due to static dis- charge by diodes to Vee and ground. Features lf Typical operating frequency: 40 MHz lf Typical propagation delay; clock to Q@: 18 ns Hi Low quiescent current: 80 pA maximum (74HC Series) @ Low input current: 1 wA maximum lf Wide power supply range: 2-6V Ordering Code: Order Number | Package Number Package Description MM74HC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.8mm Wide MM74HC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC163M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC163SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.8mm Wide MM74HC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. 1999 Fairchild Semiconductor Corporation DS005008. prf www.fairchildsemi.com Je91D SNouoIyoUAS YUM J9]UN0D Ayeulg snouoiyouds - weajg SnouoiyouASy UUM 10jUNOD Ajeulg SNOUdJYOUAS E9LOHYZININ LOLOHPZINWMM74HC161 - MM74HC163 Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP RIPPLE OUTPUTS CARRY " ENABLE Vcc OUTPUT Qq4 Qg Qc AD T LOAD | 16 16 14 13 12 "1 10 9 RIPPLEQa Qgp Qc Qp ENABLE CARRY T OUTPUT CLEAR LOAD ENABLE CK A A B c D P 1 2 3 4 5 6 7 8 CLEAR CLOCK A 8B c DO ENABLE GND $ P DATA INPUTS Logic Diagram CLEAR (181 ONLY) i 5463 oney) ~ | CLOCK Qa cK QB Truth Tables MM74HC161 CLK | CLR | ENP | ENT | Load Function x L x x x Clear x H H L H Count & RC disabled x H L H H Count disabled x H L L H Count & RC disabled tT H x x L Load tT H H H H Increment Counter MM74HC163 CLK | CLR | ENP | ENT | Load Function T L x x x Clear x H H L H Count & RC disabled x H L H H Count disabled x H L L H Count & RC disabled tT H x x L Load tT H H H H Increment Counter H = HIGH Level L= LOW Level X = Dont Care T = LOW-to-HIGH Transition Qc Qp RIPPLE CARRY www.fairchildsemi.com NoAbsolute Maximum Ratingsinote 1) Recommended Operating (Note 2) Conditions Supply Voltage (Vcc) 0.5 to +7.0V Min Max Units DC Input Voltage (Vij) 1.5 to Vect1.5V Supply Voltage (Voc) 2 6 Vv DC Output Voltage (Vour) 0.5 to Vec+0.5V DC Input or Output Voltage 0 Voc Vv Clamp Diode Current (l)x, lox) +20 mA (Vins Vout) DC Output Current, per pin (Igur) +25mA Operating Temperature Range (Ta) -40 +485 C DC Voc or GND Current, per pin (Igc) +50 mA Input Rise or Fall Times Storage Temperature Range (Tstaq) 65C to +150C (tr, t) Veo = 2.0V 1000 ns Power Dissipation (Pp) Voc =4.5 500 ns (Note 3) 600 mW Voc = 6.0V 400 ns $.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which dam- Lead Temperature age to the device may occur. (T,) (Soldering 10 seconds) 260C Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mW/C from 65C to 85C. DC Electrical Characteristics (note 4) Ta=28C Ta=40 to 85C | Ta=55 to 125C Symbol Parameter Conditions Vee Units Typ Guaranteed Limits Vin Minimum HIGH Level 2.0V 1.5 1.5 1.5 Vv Input Voltage 4.5V 3.15 3.15 3.15 Vv 6.0V 4.2 4.2 4.2 Vv VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 v Input Voltage 4.5V 1.35 1.35 1.35 Vv 6.0V 1.8 1.8 1.8 Vv Vou Minimum HIGH Level Vin= Vin or Vit Output Voltage llout| < 20 pA 2.0V 2.0 1.9 1.9 1.9 Vv 4.5V 45 44 44 44 Vv 6.0V 6.0 5.9 5.9 5.9 Vv Vin = Vin oF Vit lloutl < 4.0 mA 4.5V 4.2 3.98 3.84 3.7 Vv lloutl < 5.2 mA 6.0V 5.7 5.48 5.34 5.2 Vv VoL Maximum LOW Level Vin= Vin or Vit Output Voltage llout| < 20 pA 2.0V 0 0.1 0.1 0.1 Vv 4.5V 0 0.1 0.1 0.1 Vv 6.0V 0 0.1 0.1 0.1 Vv Vin = Vin or Vit |loutl < 4.0 mA 4.5V 0.2 0.26 0.33 0.4 Vv lloutl < 5.2 mA 6.0V 0.2 0.26 0.33 0.4 Vv lin Maximum Input Vin= Voc or GND 6.0V +0.1 +1.0 +1.0 pA Current loc Maximum Quiescent Vin= Voc or GND 6.0V 8.0 80 160 pA Supply Current lout =O pA Note 4: For a power supply of 5V +10% the worst case output voltages (Voy, and Vo_) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case Vj, and V\_ occur at Vg=5.5V and 4.5V respectively. (The V\,, value at 5.5V is 3.85V.) The worst case leakage current (lin: lee, and Igz) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com E9LOHPZINN * LOLOHPZIINMM74HC161 - MM74HC163 AC Electrical Characteristics Vec=5V, Ta= 25C, C= 15 pF, =t=6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units fax Maximum Operating Frequency 43 30 MHz tpuL, tpLy | Maximum Propagation Delay, Clock to RC 30 35 ns tpuL, tp_y | Maximum Propagation Delay, Clock to Q 29 34 ns tpyu tpty | Maximum Propagation Delay, ENT to RC 18 32 ns tPHL Maximum Propagation Delay, Clear to Q or RC 27 38 ns tREM Minimum Removal Time, Clear to Clock 10 20 ns tg Minimum Set Up Time Clear, Load, 30 ns Enable or Data to Clock ty Minimum Hold Time, Data from Clock ns tw Minimum Pulse Width Clock, 16 ns Clear, or Load AC Electrical Characteristics C_= 50 pF, t-= t=6 ns (unless otherwise specified) Ta=25C Ta=40 to 85C | Ta=-55 to 125C Symbol Parameter Conditions Vec Units Typ Guaranteed Limits fax Maximum Operating 2.0V 10 5 4 4 MHz Frequency 4.5V 40 27 21 18 MHz 6.0V 45 32 25 21 MHz tPHL Maximum Propagation 2.0V 100 215 271 320 ns Delay, Clock to RC 4.5V 32 43 54 64 ns 6.0V 28 37 46 54 ns teLH Maximum Propagation 2.0V 88 175 220 260 ns Delay, Clock to RC 4.5V 18 35 44 52 ns 6.0V 15 30 37 44 ns tPHL Maximum Propagation 2.0V 95 205 258 305 ns Delay, Clock to Q 4.5V 30 Al 52 61 ns 6.0V 26 35 44 52 ns teLH Maximum Propagation 2.0V 85 170 214 253 ns Delay, Clock to Q 4.5V 17 34 43 54 ns 6.0V 14 29 36 43 ns tPHL Maximum Propagation 2.0V 90 195 246 291 ns Delay, ENT to RC 4.5V 28 39 49 58 ns 6.0V 24 33 42 49 ns teLH Maximum Propagation 2.0V 80 160 202 238 ns Delay, ENT to RC 4.5V 16 32 40 48 ns 6.0V 14 27 34 41 ns tPHL Maximum Propagation 2.0V 100 220 275 325 ns Delay, Clear to RC 4.5V 32 44 55 66 ns 6.0V 28 37 47 55 ns tPHL Maximum Propagation 2.0V 100 210 260 315 ns Delay, Clear to Q 4.5V 32 42 52 63 ns 6.0V 28 36 45 54 ns tREM Minimum Removal 2.0V 125 158 186 ns Time Clear to Clock 4.5V 25 32 37 ns 6.0V 21 27 32 ns ts Minimum Setup 2.0V 150 190 225 ns Time Clear or Data 4.5V 30 38 45 ns to Clock 6.0V 26 32 38 ns ts Minimum Setup 2.0V 135 170 200 ns Time Load 4.5V 27 34 Al ns to Clock 6.0V 23 29 35 ns www.fairchildsemi.com 4AC Electrical Characteristics (Continueg) T,=25C T,a=40 to 85C | T,=55 to 125C Symbol Parameter Conditions Veco Units Typ Guaranteed Limits ts Minimum Setup 2.0V 175 220 260 ns Time Enable 4.5V 35 44 52 ns to Clock 6.0V 30 37 44 ns ty Minimum Hold Time 2.0V 50 63 75 ns Data from Clock 4.5V 10 13 15 ns 6.0V 9 1 13 ns ty Minimum Hold Time 2.0V 0 0 0 ns Enable, Load or Clear 4.5V 0 0 0 ns to Clock 6.0V 0 0 0 ns tw Minimum Pulse Width 2.0V 80 100 120 ns Clock, Clear, or 4.5V 16 20 24 ns Load 6.0V 14 17 20 ns tron try, = | Maximum 2.0V 40 75 95 110 ns Output Rise and 4.5V 8 15 19 22 ns Fall Time 6.0V 7 13 16 19 ns ty, t Maximum Input Rise 2.0V 1000 1000 1000 ns and Fall Time 4.5V 500 500 500 500 ns 6.0V 400 400 400 ns Cpp Powert Dissipation (per package) 90 pF Capacitance (Note 5) Cin Maximum Input Capacitance 5 10 10 10 pF Note 5: Cpp determines the no load dynamic power consumption, Pp = Cpp Veo? f+ Ie Vee, and the no load dynamic current consumption, Is = Cpp Vec f+ Ico. Logic Waveforms Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences CLEAR 161 CLEAR 163 LOAD (SYNCHRONOUS) A DATA } 8 -e-eer eer eee er er e INPUTS ae ee c ee o ee ES EE CLOCK 161 CLOCK 163 ENABLE P ENABLE T Qa QB OUTPUTS Qc Qp__ RIPPLE CARRY OUTPUT COUNT INHIBIT > CLEAR PRESET Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit 5 www.fairchildsemi.com E9LOHPZINN * LOLOHPZIINMM74HC161 - MM74HC163 Physical DimensiON$ inches (millimeters) unless otherwise noted 0.386 0,394 (9.604-10.00) 16 15 4 13 12 11 1 9 0.228-0.244 40 (5.791 6. 198) TYP TeUCUS a LEAD NO.1 7/1 2 3 4 5 6 7 8 A IDENT 0.010 pray | (0.254) | 0.150 -0.157 (3.810 3.988) 0.010-0.020 0.053 0.069. 70.2540.508) * | [~ (1.346 1.753} 0.0040.010 8 MAX TYP (0.102 0.254) ALL LEADS | 1 Eh 1 _ ee eg aed seaING . L F ; PLANE 0.008 4.010 0.014 0,050 0.0140.020 oo 0.016 0.050 0.050, gel | nq 0.914 0.020 Typ (0.203 -0.254) _ [ea06 1270) (0.356) (1.270) (0.356 - 0.508) TYP ALL LEADS 0.004 TYP ALL LEADS TYP 0.008 55 (0.102) i 203) WBA REV Hh ALL LEAD TIPS I 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16 9 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 8 0.394-0.402 0.71 0.008-0.010 (10.0-10.2) (ay? Tatscozey TP / [ \ 0.067-0.083 t iy / G.7=2.1) g-8 TYP j 0.006 (0.15) eee - SEATING tO 0.049 .| PLANE TYP | L 9.000-0.010 (G25) TYP) (0-0.25) _, 9.016-9.031 1p 0.014-0.020 11, _ ~.4=0.8) {0.35-0.50) M16D (REV B) 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M16D www.fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted (Continued) (00000007 ~~ 4.16 TYP. DIMENSIONS METRIC ONLY | se (M00 | 16 * 9 0.42 TYP ld | LULL ER EO | LAND PATTERN RECOMMENDATION GAGE PLANE fee SLE soa |_| \\ seat ie _ VU on 8 [ea] 0.2 [cB] A] TYPICAL, SCALE: 40X PIN #1 IDENT. ALL LEAD TIPS SEE DETAIL A oO p& 90) . ao a si ETT Ff (ose a ve TYP | | Lu / boa ~ 0.09-0.20 vet 0.10 + 0.05 TYP H# 0.19 - 0.30 TYP MIC16 (REV C) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com E9LOHPZINN * LOLOHPZIINMM74HC161 - MM74HC163 Synchronous Binary Counter with Asynchronous Clear - Synchronous Binary Counter with Synchronous Clear Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 = 0,780 (18.80 - 19.81) | se fe) (15) ff4) 3) 2) fi) (rol 9) INDEX AREA 0.2500.010 (6.350 0.254) PIN NO. 1 4 PIN NO. 1 IDENT IDENT OPTION 01 OPTION 02 as as 0.1300.005 0.1300.005_ 0.060 4 TYP 0.300 - 0.320 , __ Gsoze0.127) - [> rszay MP | [> oprionaL 7 (7.620- 8.128) oe 0.145 - 0.200 (3.683-5.080) } C 95 5 0.008 = 0.016 Oo oO . i! 0.020 4) 900 4 TYP (0.203 0.406) 508) 0.280 0.125 = 0.150 0.030 0.015 (7.112) (3.175 = 3.810) (0.762 40.381) MIN 0.014 = 0.023 0.100 0.010 +0.040 0.014 = 0.023 0-100 0.010 0.325 (0.356 - 0.584) soso too! (2.540 0.254) (0.525 -9'015 N16E (REV F) TP (1.270 0.254) P (8.255*1,918) TYP 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.