UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION DATE
Rev. 0.9 Original. Jan.2001
Rev. 1.0 1. The Operating Temperature is revised from Industrial temperature to
Extended temperature：-20℃~80℃
2. The symbols CE1#,OE# and WE# are revised as 1CE ,OEandWE
Jun 18,2001
Rev. 1.1 Add order information for lead free product May 15,2003
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2µA (typical) L-version
1µA (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
OperatingTemperature :
Extended : -20℃~80℃
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
1024 X 1024
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A16
Vcc
Vss
I/O1-I/O8
CE
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE,CE2 Chip enable 1,2 Inputs
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
GENERAL DESCRIPTION
The UT621024(E) is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT621024(E) is designed for low power
application. It is particularly well suited for battery
back-up nonvolatile memory application.
The UT621024(E) operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT621024(E)
PDIP / SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
NC
A16 Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT621024(E)
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
CE2
NC
A15
A16
32
31
30
29
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss VTERM -0.5 to +7.0 V
Operating Temperature Extended TA -20 to +80 ℃
Storage Temperature TSTG -65 to +150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 sec) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE CE CE2 OE WE I/O OPERATION SUPPLY CURRENT
Standby H X X X High - Z ISB,ISB1
Standby X L X X High -Z ISB,ISB1
Output Disable L H H H High - Z ICC
Read L H L H DOUT ICC
Write L H X L DIN ICC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = -20℃ to 80℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage VIH*1 2.2 - VCC+0.5 V
Input Low Voltage VIL*2 - 0.5 - 0.8 V
Input Leakage Current IIL VSS ≦VIN ≦VCC - 1 - 1 µA
Output Leakage Current IOL VSS ≦VI/O≦VCC
CE =VIH or CE2 = VIL or
OE = VIH or WE = VIL
- 1 - 1 µA
Output High Voltage VOH IOH = - 1mA 2.4 - - V
Output Low Voltage VOL IOL= 4mA - - 0.4 V
-35
-55
ICC Min.Cycle, 100% Duty,
CE =VIL, CE2 = VIH,
II/O = 0mA -70
-
-
-
60
50
40
100
85
70
mA
mA
mA
Average Operating
Power Supply Courrent
ICC1 Cycle time = 1µs, 100% Duty,
. CE≦0.2V,CE2≧VCC-0.2V,
II/O = 0Ma
- - 10 mA
ISB CE =VIH or CE2 = VIL - - 3 mA
200
- L
-
2 40*4
µA
100
Standby Power
Supply Current ISB1 CE≧VCC-0.2V or
.CE2≦0.2V - LL - 1 15*4 µA
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
4. Those parameters are for reference only under 50
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance CIN - 8 pF
Input/Output Capacitance CI/O - 10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=100pF, IOH/IOL=-1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = -20℃ to 80℃)
(1) READ CYCLE
PARAMETER
SYMBOL UT621024(E)
-35 UT621024(E)
-55 UT621024(E)
-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 35 - 55 - 70 - ns
Address Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time tACE - 35 - 55 - 70 ns
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ* - 25 - 30 - 35 ns
Output Disable to Output in High-Z tOHZ* - 25 - 30 - 35 ns
Output Hold from Address Change tOH 5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL UT621024(E)
-35 UT621024(E)
-55 UT621024(E)
-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time tWC 35 - 55 - 70 - ns
Address Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write tCW 30 - 50 - 60 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 25 - 40 - 45 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z tWHZ* - 15 - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2) tRC
tAA
Data Valid
Address
Dout
tOH tOH
Previous data valid
READ CYCLE 2 (CEand CE2 and OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tOE tOHZ
tCLZ tOH
tOLZ
High-Z D a ta Va lid High-Z
tCHZ
Address
CE2
Dout
CE
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selectedOE =low,CE =low, CE2=high.
3.Address must be valid prior to or coincident withCE =low, CE2=high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
WRITE CYCLE 1 (WE Controlled) (1,2,3,5,6)
tWC
tAW
tCW
tAS tWP
tWHZ tOW
tWR
High-Z
(4) (4)
Address
CE2
CE
WE
Dout
Din D a ta Valid
tDW tDH
WRITE CYCLE 2 (CEand CE2 Controlled) (1,2,5,6) tWC
tAW
tCW
tAS tWR
tWP
tWHZ
tDW tDH
D ata V a lid
High-Z
(4)
Address
CE2
CE
WE
Dout
Din
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
Notes :
1. WE ,CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a lowCE , high CE2, low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = -20℃ to +80℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR CE ≧ VCC-0.2V or
CE2 ≤ 0.2V 2.0 - - V
80 Data Retention Current IDR Vcc=3V - L - 1 20* µA
40
CE ≧ VCC-0.2V or
CE2 ≤ 0.2V - LL - 0.5 10* µA
Chip Disable to Data tCDR See Data Retention 0 - - ns
Retention Time Waveforms (below)
Recovery Time
tR tRC* - - ns
tRC* = Read Cycle Time
*Those parameters are for reference only under 50℃
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE controlled)
VDR ≧ 2V
CE ≧ VCC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 2V
VCC(min.)
VCC
tR
tCDR
CE2 ≦ 0.2V VIL
CE2
VCC(min.)
VIL
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
PACKAGE OUTLINE DIMENSION
32 PIN 600 mil PDIP Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A1 0.010(MIN) 0.254(MIN)
A2 0.150
±0.005 3.810
±0.127
B 0.018
±0.005 0.457
±0.127
D 1.650
±0.005 41.910
±0.127
E 0.600
±0.010 15.240
±0.254
E1 0.544
±0.004 13.818
±0.102
e 0.100 (TYP) 2.540 (TYP)
eB 0.640
±0.020 16.256
±0.508
L 0.130
±0.010 3.302
±0.254
S 0.075
±0.010 1.905
±0.254
Q1 0.070
±0.005 1.778
±0.127
NOTE:
1. D/E1/S dimension do not include mold flash.
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
32 pin 450mil SOP Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.118 (MAX) 2.997 (MAX)
A1 0.004 (MIN) 0.102 (MIN)
A2 0.111 (MAX) 2.82 (MAX)
b 0.016 (TYP) 0.406 (TYP)
D 0.817 (MAX) 20.75 (MAX)
E 0.445
±0.005 11.303
±0.127
E1 0.555
±0.012 14.097
±0.305
e 0.050 (TYP) 1.270 (TYP)
L 0.0347
±0.008 0.881
±0.203
L1 0.055
±0.008 1.397
±0.203
S 0.026 (MAX) 0.660 (MAX)
y 0.004 (MAX) 0.101 (MAX)
Θ 0o ~10o 0
o ~10o
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
32 pin TSOP-I Package Outline Dimension
HD
e
bE
"A"
1
16
32
17
Seating Plane y
C
L
16 17
132 "A" DETAIL VIEW
D
A2A1
A
L1
SEATING PLANE
0
0.254
GAUGE PLANE
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004
±0.002 0.10
±0.05
A2 0.039
±0.002 1.00
±0.05
b 0.008 + 0.002
- 0.001 0.20 + 0.05
-0.03
D 0.724
±0.004 18.40
±0.10
E 0.315
±0.004 8.00
±0.10
e 0.020 (TYP) 0.50 (TYP)
HD 0.787
±0.008 20.00
±0.20
L1 0.0315
±0.004 0.80
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16 17
32
c
L
HD
D"A"
E
e
Seating Plane y
32
17
16
1
A2A1
A
0.254
0
GAUGE PLANE
SEATING PLANE
"A" DATAIL VIEW L1
b
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004
±0.002 0.10
±0.05
A2 0.039
±0.002 1.00
±0.05
b 0.008
±0.001 0.200
±0.025
D 0.465
±0.004 11.800
±0.100
E 0.315
±0.004 8.000
±0.100
e 0.020 (TYP) 0.50 (TYP)
HD 0.528
±0.008 13.40
±0.20.
L1 0.0315
±0.004 0.80
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
ORDERING INFORMATION
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) PACKAGE
UT621024PC-35LE 35 200 32 PIN PDIP
UT621024PC-35LLE 35 100 32 PIN PDIP
UT621024SC-35LE 35 200 32 PIN SOP
UT621024SC-35LLE 35 100 32 PIN SOP
UT621024LC-35LE 35 200 32 PIN TSOP-I
UT621024LC-35LLE 35 100 32 PIN TSOP-I
UT621024LS-35LE 35 200 32 PIN STSOP
UT621024LS-35LLE 35 100 32 PIN STSOP
UT621024PC-55LE 55 200 32 PIN PDIP
UT621024PC-55LLE 55 100 32 PIN PDIP
UT621024SC-55LE 55 200 32 PIN SOP
UT621024SC-55LLE 55 100 32 PIN SOP
UT621024LC-55LE 55 200 32 PIN TSOP-I
UT621024LC-55LLE 55 100 32 PIN TSOP-I
UT621024LS-55LE 55 200 32 PIN STSOP
UT621024LS-55LLE 55 100 32 PIN STSOP
UT621024PC-70LE 70 200 32 PIN PDIP
UT621024PC-70LLE 70 100 32 PIN PDIP
UT621024SC-70LE 70 200 32 PIN SOP
UT621024SC-70LLE 70 100 32 PIN SOP
UT621024LC-70LE 70 200 32 PIN TSOP-I
UT621024LC-70LLE 70 100 32 PIN TSOP-I
UT621024LS-70LE 70 200 32 PIN STSOP
UT621024LS-70LLE 70 100 32 PIN STSOP
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
13
ORDERING INFORMATION (for lead free product)
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) PACKAGE
UT621024PCL-35LE 35 200 32 PIN PDIP
UT621024PCL-35LLE 35 100 32 PIN PDIP
UT621024SCL-35LE 35 200 32 PIN SOP
UT621024SCL-35LLE 35 100 32 PIN SOP
UT621024LCL-35LE 35 200 32 PIN TSOP-I
UT621024LCL-35LLE 35 100 32 PIN TSOP-I
UT621024LSL-35LE 35 200 32 PIN STSOP
UT621024LSL-35LLE 35 100 32 PIN STSOP
UT621024PCL-55LE 55 200 32 PIN PDIP
UT621024PCL-55LLE 55 100 32 PIN PDIP
UT621024SCL-55LE 55 200 32 PIN SOP
UT621024SCL-55LLE 55 100 32 PIN SOP
UT621024LCL-55LE 55 200 32 PIN TSOP-I
UT621024LCL-55LLE 55 100 32 PIN TSOP-I
UT621024LSL-55LE 55 200 32 PIN STSOP
UT621024LSL-55LLE 55 100 32 PIN STSOP
UT621024PCL-70LE 70 200 32 PIN PDIP
UT621024PCL-70LLE 70 100 32 PIN PDIP
UT621024SCL-70LE 70 200 32 PIN SOP
UT621024SCL-70LLE 70 100 32 PIN SOP
UT621024LCL-70LE 70 200 32 PIN TSOP-I
UT621024LCL-70LLE 70 100 32 PIN TSOP-I
UT621024LSL-70LE 70 200 32 PIN STSOP
UT621024LSL-70LLE 70 100 32 PIN STSOP
UTRON UT621024(E)
Rev. 1.1 128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80037
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
14
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